Abstract
Demand for fast dynamic reconfiguration has increased since dynamic reconfiguration can accelerate the performance of implementation circuits. Such dynamic reconfiguration requires two important features: fast reconfiguration and numerous contexts. However, fast reconfigurations and numerous contexts share a trade-off relation on current VLSIs. Therefore, optically reconfigurable gate arrays (ORGAs) have been developed to resolve this dilemma. ORGAs can realize a large virtual gate count that is much larger than those of current VLSI chips by exploiting the large storage capacity of a holographic memory. Also, ORGAs can realize fast reconfiguration through use of large bandwidth optical connections between a holographic memory and a programmable gate array VLSI. Among such developments, we have been developing dynamic optically reconfigurable gate arrays (DORGAs) that realize a high gate density VLSI using a photodiode memory architecture. This paper presents the first demonstration of a nine-context DORGA architecture. Furthermore, this paper presents experimental results: 1.2-8.97μs reconfiguration times and 66-221μs retention times.
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References
Altera Corporation, Altera Devices, http://www.altera.com
Xilinx Inc., Xilinx Product Data Sheets, http://www.xilinx.com
Lattice Semiconductor Corporation, LatticeECP and EC Family Data Sheet (2005), http://www.latticesemi.co.jp/products
Nakano, H., Shindo, T., Kazami, T., Motomura, M.: Development of dynamically reconfigurable processor LSI. NEC Tech. J (Japan) 56(4), 99–102 (2003)
Dehon, A.: Dynamically Programmable Gate Arrays: A Step Toward Increased Computational Density. In: Fourth Canadian Workshop on Field Programmable Devices, pp. 47–54 (1996)
Scalera, S.M., Vazquez, J.R.: The design and implementation of a context switching FPGA. In: IEEE symposium on FPGAs for Custom Computing Machines, pp. 78–85 (1998)
Trimberger, S., et al.: A Time–Multiplexed FPGA. In: FCCM, pp. 22–28 (1997)
Jones, D., Lewis, D.M.: A time–multiplexed FPGA architecture for logic emulation. In: Custom Integrated Circuits Conference, pp. 495–498 (1995)
Mumbru, J., Panotopoulos, G., Psaltis, D., An, X., Mok, F., Ay, S., Barna, S., Fossum, E.: Optically Programmable Gate Array. In: SPIE of Optics in Computing 2000, vol. 4089, pp. 763–771 (2000)
Mumbru, J., Zhou, G., An, X., Liu, W., Panotopoulos, G., Mok, F., Psaltis, D.: Optical memory for computing and information processing. In: SPIE on Algorithms, Devices, and Systems for Optical Information Processing III, vol. 3804, pp. 14–24 (1999)
Mumbru, J., Zhou, G., Ay, S., An, X., Panotopoulos, G., Mok, F., Psaltis, D.: Optically Reconfigurable Processors. In: SPIE Critical Review 1999 Euro-American Workshop on Optoelectronic Information Processing, vol. 74, pp. 265–288 (1999)
Watanabe, M., Kobayashi, F.: An Optically Differential Reconfigurable Gate Array using a 0.18 um CMOS process. In: IEEE International SOC Conference, pp. 281–284 (2004)
Watanabe, M., Shiki, T., Kobayashi, F.: 272 gate count optically differential reconfigurable gate array VLSI. In: International Conference on engineering of reconfigurable systems and algorithms (2007) (CD-ROM)
Watanabe, M., Kobayashi, F.: An optical reconfiguration circuit for optically reconfigurable Gate Arrays. In: 2004 IEEE International Midwest Symposium on Circuits and Systems, pp. I-529–I-532 (2004)
Watanabe, M., Kobayashi, F.: A 16,000-gate-count Optically Reconfigurable Gate Array in a standard 0.35um CMOS Technology. In: IEEE International Symposium on Circuits and Systems (2005)
Watanabe, M., Kobayashi, F.: A high-density optically reconfigurable gate array using dynamic method. In: International conference on Field-Programmable Logic and its Applications, pp. 261–269 (2004)
Watanabe, M., Kobayashi, F.: A dynamic optically reconfigurable gate array using dynamic method. In: International Workshop on Applied Reconfigurable Computing, pp. 50–58 (2005)
Watanabe, M., Kobayashi, F.: A 51,272-gate-count Dynamic Optically Reconfigurable Gate Array in a standard 0.35um CMOS Technology. In: International Conference on Solid State Devices and Materials, pp. 336–337 (2005)
Watanabe, M., Kobayashi, F.: A Dynamic Optically Reconfigurable Gate Array. Japanese Journal of Applied Physics 45(4B), 3510–3515 (2006)
Seto, D., Watanabe, M.: Reconfiguration performance analysis of a dynamic@optically reconfigurable gate array architecture. In: IEEE International Conference on Field Programmable Technology, pp. 265–268 (2007)
Nakajima, M., Watanabe, M.: A 770ns holographic reconfiguration of a four-contexts DORGA. In: International Conference on engineering of reconfigurable systems and algorithms, pp. 289–292 (July 2008)
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Nakajima, M., Watanabe, M. (2009). Fast Optical Reconfiguration of a Nine-Context DORGA. In: Becker, J., Woods, R., Athanas, P., Morgan, F. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2009. Lecture Notes in Computer Science, vol 5453. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-00641-8_14
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DOI: https://doi.org/10.1007/978-3-642-00641-8_14
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