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Negation-Limited Inverters of Linear Size

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Algorithms and Computation (ISAAC 2008)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 5369))

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Abstract

An inverter is a circuit which outputs ¬x 1, ¬x 2, ..., ¬x n for any Boolean inputs x 1, x 2, ..., x n . Beals, Nishino and Tanaka have given a construction of an inverter which has size O(nlogn) and depth O(logn) and uses ⌈log(n + 1) ⌉ NOT gates. In this paper we give a construction of an inverter which has size O(n) and depth log1 + o(1) n and uses log1 + o(1) n NOT gates. This is the first negation-limited inverter of linear size using only o(n) NOT gates.

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Author information

Authors and Affiliations

  1. Graduate School of Information Sciences, Tohoku University, Sendai, 980-8579, Japan

    Hiroki Morizumi

  2. School of Engineering, Tohoku University, Sendai, 980-8579, Japan

    Genki Suzuki

Authors
  1. Hiroki Morizumi
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  2. Genki Suzuki
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Editor information

Editors and Affiliations

  1. School of Information Technologies, University of Sydney, Australia

    Seok-Hee Hong

  2. Graduate School of Informatics, Kyoto University, 606-8501, Kyoto, Japan

    Hiroshi Nagamochi

  3. Graduate School of Informatics, Kyoto University, Japan

    Takuro Fukunaga

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Morizumi, H., Suzuki, G. (2008). Negation-Limited Inverters of Linear Size. In: Hong, SH., Nagamochi, H., Fukunaga, T. (eds) Algorithms and Computation. ISAAC 2008. Lecture Notes in Computer Science, vol 5369. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-92182-0_54

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  • DOI: https://doi.org/10.1007/978-3-540-92182-0_54

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-92181-3

  • Online ISBN: 978-3-540-92182-0

  • eBook Packages: Computer ScienceComputer Science (R0)

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