Abstract
This paper presents a network architecture to interconnect mixed-signal VLSI integrate-and-fire neural networks in a way that the timing of the neural network data is preserved. The architecture uses isochronous connections to reserve network bandwidth and is optimized for the small data event packets that have to be exchanged in spiking hardware neural networks. End-to-end delay is reduced to the minimum by retaining 100% throughput. As buffering is avoided wherever possible, the resulting jitter is independent of the number of neural network chips used. This allows to experiment with neural networks of thousands of artificial neurons with a speedup of up to 105 compared to biology. Simulation results are presented. The work focuses on the interconnection of hardware neural networks. In addition to this, the proposed architecture is suitable for any application where bandwidth requirements are known and constant low delay is needed.
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References
The Neural Simulation Technology (NEST) Initiative (2007), Homepage, http://www.nest-initiative.org
Schemmel, J., Hohmann, S., Meier, K., Schürmann, F.: A mixed-mode analog neural network using current-steering synapses. Analog Integrated Circuits and Signal Processing 38(2-3), 233–244 (2004)
Indiveri, G., Chicca, E., Douglas, R.: A VLSI array of low-power spiking neurons and bistable synapses with spike–timing dependent plasticity. IEEE Transactions on Neural Networks 17(1), 211–221 (2006)
Schemmel, J., Grübl, A., Meier, K., Mueller, E.: Implementing synaptic plasticity in a VLSI spiking neural network model. In: Proceedings of the 2006 International Joint Conference on Neural Networks (IJCNN’06), Orlando, IEEE Press, Los Alamitos (2006)
Fieres, J., Grübl, A., Philipp, S., Meier, K., Schemmel, J., Schürmann, F.: A platform for parallel operation of VLSI neural networks. In: Proc. of the 2004 Brain Inspired Cognitive Systems Conference, BICS2004 (2004)
Tanenbaum, A.S.: Computer Networks. Pearson Education Int., London (2004)
Hung, A., Kesidis, G., McKeown, N.: ATM input-buffered switches with guaranteed-rate property. In: Proc. of IEEE ISCC’98, Athens, pp. 331–335 (1998)
Li, S., Ansari, N.: Input-queued switching with QoS guarantees. In: Proceedings of IEEE INFOCOM’99, New York, pp. 1152–1159 (1999)
Xilinx, Inc.: Virtex-II Pro Platform FPGA Handbook (2002), http://www.xilinx.com
Xilinx, Inc.: RocketIO Ttransceiver User Guide (2003), http://www.xilinx.com
Xilinx, Inc.: Xilinx Application Note 670, Minimizing Receiver Elastic Buffer Delay in the Virtex-II Pro RocketIO Transceiver (2003), http://www.xilinx.com
Brélaz, D.: New methods to color the vertices of a graph. Commun. ACM 22(4), 251–256 (1979)
Ehrlich, M., Mayr, C., Eisenreich, H., Henker, S., Srowig, A., Grübl, A., Schemmel, J., Schüffny, R.: Wafer-Scale VLSI implementations of pulse coupled neural networks. In: Proc. of IEEE SSD07, Hammamet, Tunisia (March 2007)
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Philipp, S., Grübl, A., Meier, K., Schemmel, J. (2007). Interconnecting VLSI Spiking Neural Networks Using Isochronous Connections. In: Sandoval, F., Prieto, A., Cabestany, J., Graña, M. (eds) Computational and Ambient Intelligence. IWANN 2007. Lecture Notes in Computer Science, vol 4507. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-73007-1_58
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DOI: https://doi.org/10.1007/978-3-540-73007-1_58
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-73006-4
Online ISBN: 978-3-540-73007-1
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