Abstract
Recently, computerized testing has revolutionized the testing industry by offering an array of benefits for both the examinees and the test users. It potentially enhances the quality of education at all levels. Computerized testing also makes available new types of data such as item-response time and human response at the individual item level. However, the present models of these responses demand much computing time. This paper presents an analysis for a parallel implementation of the models by estimating parallel speedup and efficiency. The model provides an insight into the success of advanced computerized testing study using high performance computing (HPC) technology.
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Wang, T., Ni, J. (2007). Speedup Analysis for Parallel Implementation of Model of Response Accuracy and Response Time in Computerized Testing. In: Shi, Y., van Albada, G.D., Dongarra, J., Sloot, P.M.A. (eds) Computational Science – ICCS 2007. ICCS 2007. Lecture Notes in Computer Science, vol 4489. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-72588-6_5
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DOI: https://doi.org/10.1007/978-3-540-72588-6_5
Publisher Name: Springer, Berlin, Heidelberg
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