Abstract
Settling time is one of the most important performance parameters for a whole class of amplifier, such as those employed in switched-capacitor-based circuits and analog-to-digital converters. In this work, analysis to predict and to minimize the settling time for amplifiers characterized by first-, second-, and third-order system-wise behaviour, is developed. The proposed method is very useful for design purposes. It allows amplifier poles to be placed directly in the complex plane, achieving the best-settled time response in accord with the desired accuracy level.
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Pugliese, A., Cappuccino, G., Cocorullo, G. (2007). Settling Time Minimization of Operational Amplifiers. In: Azémard, N., Svensson, L. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2007. Lecture Notes in Computer Science, vol 4644. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-74442-9_11
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DOI: https://doi.org/10.1007/978-3-540-74442-9_11
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-74441-2
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