Abstract
This paper presents an efficient synchronous pipeline hardware implementation procedure for a neuro-fuzzy (NF) circuit. We decompose the NF circuit into a feedforward circuit and a backpropagation circuit. The concept of pre-calculation to share computation results between the feedforward circuit and backpropagation circuit is introduced to achieve a high throughput rate and low resource usage. A novel pipeline architecture has been adopted to fulfill the concept of pre-calculation. With the unique pipeline architecture, we have successfully enhanced the throughput rate and resource sharing between modules. Particularly, the multiplier usage has been reduced from 7 to 3 and the divider usage from 3 to 1. Finally, we have implemented the NF circuit on FGPA. Our experimental results show a superior performance than that of an asynchronous pipeline design approach and the NF system implemented on MATLAB®.
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References
Wang, J.-S., Lee, C.-S.G.: Self-Adaptive Neuro-Fuzzy Inference Systems for Classifications Applications. IEEE Trans. on Fuzzy Systems 10(6), 790–802 (2002)
Wang, J.-S., Lee, C.-S.G.: Self-Adaptive Recurrent Neuro-Fuzzy Control of an Autonomous Underwater Vehicle. IEEE Trans. on Robotics and Automation 19(2), 283–295 (2003)
Rubaai, A., Kotaru, R., Kankam, M.D.: A Continually Online-Trained Neural Network Controller for Brushless DC MotorDrives. IEEE Trans. on Industry Applications 36(2), 475–483 (2000)
Micheli, G.-D.: Synthesis and Optimization of Digital Circuits. McGraw-Hill, Newyork (1994)
Wang, Q., Yi, B., Xie, Y., Liu, B.: The Hardware Structure Design of Perceptron with FPGA Implementation. In: Proc. of the IEEE Int. Conf. on Systems, Man and Cybernetics vol. 1, pp. 762–767 (2003)
Porrmann, M., Witkowski, U., Kalte, H., Ruckert, U.: Implementation of Artificial Neural Networks on a Reconfigurable Hardware Accelerator. In: Proc. of 10th Euromicro Workshop on Parallel, Distributed and Network-based Processing, pp. 243–250 (2002)
Vitabile, S., Conti, V., Gennaro, F., Sorbello, F.: Efficient MLP Digital Implementation on FPGA. In: Proc. of 8th Euromicro Conf. on Digital System Design, pp. 218–222 (2005)
Togai, M., Watanabe, H.: Expert System on a Chip: An Engine for Real-Time Approximate Reasoning. IEEE Expert 1(3), 55–62 (1986)
Jou, J.-M., Chen, P.-Y., Yang, S.-F.: An Adaptive Fuzzy Logic Controller: Its VLSI Architecture and Applications. IEEE Trans. on VLSI Systems 8(1), 52–60 (2000)
Juang, C.-F., Hus, C.-H.: Temperature Control by Chip-Implemented Adaptive Recurrent Fuzzy Controller Designed by Evolutionary Algorithm. IEEE Trans. on Circuits and Systems 52(11), 2376–2384 (2005)
Juang, C.-F., Chen, J.-S.: Water Bath Temperature Control by a Recurrent Fuzzy Controller and its FPGA Implementation. IEEE Trans. on Industrial Electronics 53(3), 941–949 (2006)
Hwang, C.-T., Lee, J.-H., Hsu, Y.-C.: A Formal Approach to the Scheduling Problem in High Level Synthesis. IEEE Trans. on Computer-Aided Design 10(4), 464–475 (1991)
Paulin, P.G., Knight, J.P.: Algorithm for High-Level Synthesis. IEEE Trans. on Design & Test of Computers 6(6), 18–31 (1989)
Gajski, D., Wu, A., Dutt, N., Lin, S.: High-level Synthesis: Introduction to Chip and System Design. Kluwer Academic, Boston (1992)
Mitra, S., Hayashi, Y.: Neuro-Fuzzy Rule Generation: Survey in Soft Computing Framework. IEEE Trans. on Neural Networks 11(3), 748–768 (2000)
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Lin, CW., Wang, JS., Yu, CC., Chen, TY. (2007). Synchronous Pipeline Circuit Design for an Adaptive Neuro-fuzzy Network. In: Huang, DS., Heutte, L., Loog, M. (eds) Advanced Intelligent Computing Theories and Applications. With Aspects of Artificial Intelligence. ICIC 2007. Lecture Notes in Computer Science(), vol 4682. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-74205-0_19
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DOI: https://doi.org/10.1007/978-3-540-74205-0_19
Publisher Name: Springer, Berlin, Heidelberg
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