Rethinking Computer Architecture Research

The prevailing methodology in architecture research is to propose a mechanism, incorporate it in some existing execution-driven software simulator and collect statistics related to some standard benchmarks to determine the merits of the architectural proposal. In recent architecture conferences as many as ninety five percent of the papers have followed this methodology.

Some of the pitfalls of this approach are well known: frequent omissions (either deliberately or inadvertently) of important aspects of the system, total disregard for implementation complexity, inability to model time accurately in situations where interactions are nondeterministic and thus, potentially deeply affected by timing assumptions, and inability to run realistic applications with large enough data sets, especially in parallel systems. Architects of real systems have generally ignored such simulation studies because of aforementioned weaknesses. They are driven primarily by constraints such as power and clock speeds, and by compatibility with their own older systems. The relative importance of these constraints changes from time to time and sometimes that can affect the microarchitecture under consideration. For example, the next generation technology will offer so much variability in power and speed that it may require us to reconsider the whole notion of “timing closure”.

There are two new developments that together enables a more “implementation aware” study of microarchitectures. Availability of FPGA’s with as many as 6-million gates, multiple RISC cores and 256K bytes of memory make it possible to implement very complex devices (e.g., a complex 64-bit processor) on a single FPGA. Furthermore, high-level synthesis tools, such as Bluespec, make it possible for a small team to generate RTL for complex devices within a matter of weeks, if not days. A proper setup with FPGA’s and high-level synthesis tools can enable universities to architectural studies that are much more rewarding and useful than pure software simulations. The same high-level synthesis techniques can also be directed toward ASICs and custom circuits where physical layout and other backend issues can be considered.

We will illustrate this new style of “implementation aware” research through several ongoing projects at MIT and CMU.

Authors and Affiliations

1. Computer Science and Artificial Intelligence Laboratory (CSAIL), Massachusetts Institute of Technology, USA

   Arvind

Editors and Affiliations

1. IRISA/ENS Cachan, Campus de Beaulieu, 35042, Rennes Cedex, France

   Luc Bougé

2. Department of Electrical Engineering, University of Southern California, 90089-2562, Los Angeles, CA, USA

   Viktor K. Prasanna

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