Abstract
Telecommunication applications integrate more and more functionalities, and a huge capacity of memory is required; as a result power consumption increases and battery lifetime becomes a serious limitation. An other consequence is that the time to realize such systems becomes too long! This paper presents methods to optimize consumption/time for HW/SW codesign. Then, a refinement step is executed to optimize the schedulings by applying the Dynamic Voltage Scaling/ Dynamic Frequency Scaling technique (DVS/DFS), and founding the best distribution of data between internal memory and external memory in order to decrease the global consumption. The novelty of our work consists in taking into account the consumption parameter during the allocation and scheduling steps; refining the scheduling by exploiting the DVS technique; optimizing the system memory consumption by improving the data storage in internal memory of the processor.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Dick, R.P., Jha, N.K.: MOCSYN: Multiobjective core-based single-chip system synthesis. In: Proc. Design Automation &Test in Europe Conf., March 1999, pp. 263–227 (1999)
Dave, B.P., Lakshminarayana, G., Jha, N.K.: COSYN: Hardware-Software Co- Synthesis of Heterogeneous Distributed Embedded Systems in proceedings of Design Automation Conference, California, pp. 703–708 (1997)
Chou, P.H., Liu, J., Li, D., Bagherzadeh, N.: IMPACCT: Methodology and Tools for Power-Aware Embedded Systems. In: Design Automation for Embedded Systems, pp. 7-205-232. Kluwer Academic Publishers, Dordrecht (2002)
Liu, J., Chou, P.H., Aboughazaleh, N., Kurdahi, F.: A Constraint-based Application Model and Scheduling Techniques for Power-aware Systems. In: Proceedings of the Ninth International Symposium on Hardware/Software Codesign CODES 2001, Copenhagen, Denmark, p. 153 (2001)
AbouGhazaleh, N., Mossé, D., Childers, B., Melhem, R.: Toward The Placement of Power Manegement Points in Real Time Applications. In: COLP 2001 (Workshop on Compilers and Operating Systems for Low Power), Barcelona, Spain (2001)
Mossé, D., Aydin, H., Childers, B., Melhem, R.: Compiler-Assisted Dynamic Power-Aware Scheduling for Real-Time Applications. In: Workshop on Compilers and Operating Systems for Low Power (October 2000)
Kamble, M., Ghose, K.: Modeling energy dissipation in low power caches. Technical Repport, CS-TR-98-02, Departement of computer science, SUNY6Binghamton (1998)
Catthoor, F., de Greef, E., Suytack, S.: Custom memory management methodology: Exploration of memory organisation for embedded multimedia system design. Kluwer Academic Publishers, Dordrecht (1998) ISBN 0-7923-8288-9
Corre, G., Julien, N., Senn, E., Martin, E.: Optimisation de la consommation des unités de mémorisation lors de la synthèse d’architecture, 3ème Colloque de CAO de Circuits et Systèmes Intégrés, Paris (Mai 2002)
Guitton-Ouhamou, P., Belleudy, C., Auguin, M.: Power consumption Model for the DSP OAK Processor. In: Proceedings of 11th IFIP International Conference on Very Large Scale Integration- System-On Chip 2001, Montpellier, France, pp. 73–78 (2001)
Auguin, M., Capella, L., Cuesta, F., Gresset, E.: CODEF: A System Level Design Space Exploration Tool, Sophia-Antipolis forum on MicroElectronics. In: SAME 2000, France (2000)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2004 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Guitton-Ouhamou, P., Fradj, H.B., Belleudy, C., Auguin, M. (2004). Low Power Co-design Tool and Power Optimization of Schedules and Memory System. In: Macii, E., Paliouras, V., Koufopavlou, O. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2004. Lecture Notes in Computer Science, vol 3254. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30205-6_62
Download citation
DOI: https://doi.org/10.1007/978-3-540-30205-6_62
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-23095-3
Online ISBN: 978-3-540-30205-6
eBook Packages: Springer Book Archive