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Loop Scheduling for Real-Time DSPs with Minimum Switching Activities on Multiple-Functional-Unit Architectures

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Embedded and Ubiquitous Computing (EUC 2004)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 3207))

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Abstract

This paper studies the scheduling problem that minimizes both schedule length and switching activities for applications with loops on multiple-functional-unit architectures. We formally prove that to find a schedule that has the minimal switching activities among all minimum-latency schedules with or without resource constraints is NP-complete. An algorithm, SAMLS (Switching-Activity Minimization Loop Scheduling), is proposed to minimize both schedule length and switching activities. In SAMLS, the best schedule is selected from the ones generated from a given initial schedule by repeatedly rescheduling the nodes with schedule length and switching activities minimization based on rotation scheduling and bipartite matching. The experimental results show our algorithm can greatly reduce both schedule length and switching activities compared with the previous work.

This work is partially supported by TI University Program, NSF EIA-0103709, Texas ARP 009741-0028-2001, NSF CCR-0309461, USA, and HK POLYU A-PF86 and COMP 4-Z077, HK.

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References

  1. Kim, D., Shin, D., Choi, K.: Low Power of Linear Systems: A Common Operand Centric Approach. In: IEEE/ACM Int. Symp. on Low Power Electronics and Design, pp. 225–230 (2001)

    Google Scholar 

  2. Yu, T., Chen, F., Sha, E.: Loop Scheduling Algorithms for Power Reduction. In: IEEE Int. Conf. on Acoustics, Speech, and Signal Processing, pp. 3073–3076 (1998)

    Google Scholar 

  3. Raghunathan, A., Jha, N.: An ILP formulation for low power based on minimizing switched capacitance during data path allocation. In: IEEE Int. Symp. on Circuits & Systems, pp. 1069–1073 (1995)

    Google Scholar 

  4. Musoll, E., Cortadella, J.: Scheduling and resource binding for low power. In: IEEE Int. Symp. on System Synthesis, pp. 104–109 (1995)

    Google Scholar 

  5. Chandrakasan, A., Sheng, S., Brodersen, R.: Low-Power CMOS Digital Design. IEEE Journal of Solid-State Circuits 27(4) (1992)

    Google Scholar 

  6. Lee, C., Lee, J., Hwang, T., Tsai, S.: Compiler optimization on VLIW instruction scheduling for low power. ACM Transactions on Design Automation of Electronic Systems 8(2), 252–268 (2003)

    Article  Google Scholar 

  7. Chao, L., LaPaugh, A., Sha, E.: Rotation Scheduling: A Loop Pipelining Algorithm. IEEE Trans. on Computer-Aided Design 16(3), 229–239 (1997)

    Article  Google Scholar 

  8. Shao, Z., Zhuge, Q., Sha, E., Chantrapornchai, C.: Loop Scheduling for Minimizing Schedule Length and Switching Activities. In: IEEE Int. Symp. on Circuits and Systems, vol. V, 109–112 (2003)

    Google Scholar 

  9. Yang, H., Gao, G., Leung, C.: On achieving balanced power consumption in software pipelined loops. In: Int. Conf. on Compilers, Architectures and Synthesis for Embedded Systems, pp. 210–217 (2002)

    Google Scholar 

  10. Yun, H., Kim, J.: Power-aware modulo scheduling for high-performance VLIW processors. In: Int. Symp. on Low power electronics and design, pp. 40–45 (2001)

    Google Scholar 

  11. Leiserson, C., Saxe, J.: Retiming Synchronous Circuitry. Algorithmica 6, 5–35 (1991)

    Article  MATH  MathSciNet  Google Scholar 

  12. Garey, M., Johnson, D.: Computers and Intractability: A Guide to the Theory of NP-Completeness. W.H. Freeman and Company, New York (1979)

    MATH  Google Scholar 

  13. Garey, M., Johnson, D.: Some NP-complete Geometric Problems. ACM Symp. on Theory of Computing, 10–22 (1976)

    Google Scholar 

  14. Shao, Z., Sha, E.: Switching-Activity Minimization on Instruction-level Loop Scheduling for VLIW DSP Applications. Tech. Report (TR-0601-HSCL-UTD) University of Texas at Dallas (2004)

    Google Scholar 

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© 2004 Springer-Verlag Berlin Heidelberg

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Shao, Z., Zhuge, Q., Liu, M., Sha, E.H.M., Xiao, B. (2004). Loop Scheduling for Real-Time DSPs with Minimum Switching Activities on Multiple-Functional-Unit Architectures. In: Yang, L.T., Guo, M., Gao, G.R., Jha, N.K. (eds) Embedded and Ubiquitous Computing. EUC 2004. Lecture Notes in Computer Science, vol 3207. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30121-9_6

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  • DOI: https://doi.org/10.1007/978-3-540-30121-9_6

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-22906-3

  • Online ISBN: 978-3-540-30121-9

  • eBook Packages: Springer Book Archive

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