Abstract
The study of interconnects in VLSI circuit is becoming a crucial issue. A model for energy calculation is developed. An study of the different contributions to energy dissipation through electrical simulation for several interconnect structures and different driver strengths is also performed. The main goal is to compare the different contributions related to the aspects mentioned above. The importance of the interconnect contribution in the energy dissipation of the chip is analyzed in a 0.18μm CMOS technology showing its relevance even for not very long lines.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Werner, C., Göttsche, R., Wörner, A., Ramacher, U.: Crosstalk Noise in Future Digital CMOS Circuits. In: IEEE Design Automation Test Europe DATE 2001 (2001)
Chandrakasan, A.P., Brodersen, R.W.: Low Power Digital CMOS Design. Kluwer Academic Publishers, Dordrecht (1995)
Caignet, F., Delmas, S., Sicard, E.: The Challenge of Signal Integrity in Deep- Submicrometer CMOS Technology. Proc. of the IEEE 89(4), 556–573 (2001)
Choi, S.H., Paul, B.C., Roy, K.: Dynamic Noise Analysis with Capacitive and Inductive Coupling. In: Proceedings of the 15th International Conference on VLSI Design (2002)
Roca, M., Moll, F., Rubio, A.: Electric design rules for avoiding crosstalk in microelectronic circuits. In: PATMOS 1994, October 1994, pp. 76–83 (1994)
Moll, F., Roca, M., Rubio, E., Sicard, E.: Analysis and measurement of crosstalk induced delay errors in integrated circuits. In: Grabinsky, H., Nordholz, P. (eds.) Signal Propagation of Interconnects, ch. 12, pp. 139–147. Kluwer Academic Publishers, Dordrecht (1998)
Sotiradis, P.P., Chandrasakan, A.: Bus Energy Minimization by Transition Pattern Coding (TPC) in Deep Submicron Technologies. In: ICCAD (November 2000)
Kim, K.W., Jung, S.O., Narayanan, U., Liu, C.L., Kang, S.M.: Noise-Aware Power Optimization for On-Chip Interconnect. In: Proc. ISLPED 2000 (2000)
Kim, K.W., Baek, K.H., Shanbhag, N., Liu, C.L., Kang, S.M.: Coupling-driven signal encoding scheme for low-power interface design. In: ICCAD (November 2000)
Machiarulo, L., Macii, E., Poncino, M.: Wire placement for crosstalk energy minimization in address buses. In: Design Automation and Test in Europe DATE 2002 (2002)
Raphael Reference Manual, Avant! Corporation (December 1998)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2003 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Isern, E., Roca, M., Moll, F. (2003). Analysis of the Contribution of Interconnect Effects in Energy Dissipation of VLSI Circuits. In: Chico, J.J., Macii, E. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2003. Lecture Notes in Computer Science, vol 2799. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39762-5_54
Download citation
DOI: https://doi.org/10.1007/978-3-540-39762-5_54
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-20074-1
Online ISBN: 978-3-540-39762-5
eBook Packages: Springer Book Archive