Abstract
As technology scales, energy consumption is becoming an important issue in high-performance VLSI microprocessor designs. Often the critical path of these microprocessors is in the datapath of arithmetic units, resulting in high energy consumption along the datapath. We propose an optimization method that can achieve energy saving versus delay-based optimization at equal performance. It reveals that the source of energy saving lays in the balance of delay and energy consumption among different stages of a circuit. The energy saving is significant, 30%(50%. The results are confirmed with simulation, using Fujitsu’s 0.11μm, 1.2V CMOS technology.
This work has been supported by SRC Research Grant No. 931.001, Fujitsu Laboratories of America and California MICRO 02-057.
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Dao, H.Q., Zeydel, B.R., Oklobdzija, V.G. (2003). Energy Optimization of High-Performance Circuits. In: Chico, J.J., Macii, E. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2003. Lecture Notes in Computer Science, vol 2799. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39762-5_46
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DOI: https://doi.org/10.1007/978-3-540-39762-5_46
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