Abstract
The reservoir computation (RC) is a recurrent neural network architecture that is very suitable for time series prediction tasks. Its implementation in specific hardware can be very useful in relation to software approaches, especially when low consumption is an essential requirement. However, the hardware realization of RC systems is expensive in terms of circuit area and power dissipation, mainly due to the need of a large number of multipliers at the synapses. In this paper, we present an implementation of an RC network with cyclic topology (simple cyclic reservoir) in which we limit the available synapses’ weights, which makes it possible to replace the multiplications with simple addition operations. This design is evaluated to implement the equalization of a non-linear communication channel, and allows significant savings in terms of hardware resources, presenting an accuracy comparable to previous works.
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Acknowledgment
This work has been partially supported by the Spanish Ministry of Economy and Competitiveness (MINECO), the Regional European Development Funds (FEDER), and the Comunitat Autonoma de les Illes Balears under grant contracts TEC2014-56244-R, TEC2017-84877-R and a fellowship (FPI/1513/2012) financed by the European Social Fund (ESF) and the Govern de les Illes Balears (Conselleria d’Educació, Cultura i Universitats).
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Skibinsky-Gitlin, E.S. et al. (2018). Cyclic Reservoir Computing with FPGA Devices for Efficient Channel Equalization. In: Rutkowski, L., Scherer, R., Korytkowski, M., Pedrycz, W., Tadeusiewicz, R., Zurada, J. (eds) Artificial Intelligence and Soft Computing. ICAISC 2018. Lecture Notes in Computer Science(), vol 10841. Springer, Cham. https://doi.org/10.1007/978-3-319-91253-0_22
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