Abstract
Adders, being one of the fundamental operators in many processing applications, have received a significant amount of attention in approximate computing. Using approximate low-power and low-latency adders can have a significant effect on improving the energy efficiency and performance of a system, at the cost of reasonable accuracy loss. For this chapter, we restrict our focus towards generic configurable models for high-performance (low-latency) approximate adders. These models provide design time support for choosing appropriate low-latency approximate adder design, which offers desired level of quality while providing optimal performance. In this chapter, we also cover the mathematical analysis which shows that, provided a latency constraint, an adder configuration with the highest quality and lowest area/power requirement can effortlessly be selected from the complete design space of low-latency adders. Towards the end of the chapter, we present extensive results in support of the presented mathematical analysis and show that the selected optimal configurations indeed provide optimal results even in real-world applications.
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Hanif, M.A., Hafiz, R., Shafique, M. (2019). Configurable Models and Design Space Exploration for Low-Latency Approximate Adders. In: Reda, S., Shafique, M. (eds) Approximate Circuits. Springer, Cham. https://doi.org/10.1007/978-3-319-99322-5_1
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DOI: https://doi.org/10.1007/978-3-319-99322-5_1
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