Abstract
In this paper the issue of optimizing memory bandwidth to external RAM in FPGA hardware implementation of foreground object segmentation methods is discussed. Three representative background modelling algorithms: Running Average (RA), Gaussian Mixture Model (GMM) and Pixel Based Adaptive Segmenter (PBAS) and three lossless compression methods: Run Length Encoding (RLE), Huffman coding and Hierarchical Average and Copy Prediction (HACP) with Significant Bit Truncation (SBT) coding were considered. After initial simulations in a software model, it was decided to implement the HACP+SBT approach in hardware. In addition, the possibility of using the proposed solution for ultra high-definition video stream processing was evaluated.
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The work presented in this paper was supported by the National Science Centre project no. 2016/23/D/ST6/01389.
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Piszczek, K., Janus, P., Kryjak, T. (2018). The Use of HACP+SBT Lossless Compression in Optimizing Memory Bandwidth Requirement for Hardware Implementation of Background Modelling Algorithms. In: Voros, N., Huebner, M., Keramidas, G., Goehringer, D., Antonopoulos, C., Diniz, P. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2018. Lecture Notes in Computer Science(), vol 10824. Springer, Cham. https://doi.org/10.1007/978-3-319-78890-6_31
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