Abstract
This paper proposes an efficient reversible synthesis for the \(n\)-to-2\(^n\) sequence counter, where \(n\ge \) 2 and \(n \epsilon \) \(N\). The proposed circuits are designed using only reversible fault tolerant gates. Thus, the entire circuit inherently becomes fault tolerant. In addition, an algorithm to design the \(n\)-to-2\(^n\) reversible fault tolerant sequence counter based on fault tolerant J-K flip-flops has been presented. The functional verification of the proposed circuit is completed through the simulation results. Moreover, the comparative results show that the proposed method performs much better and is much more scalable than the existing approaches.
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Shamsujjoha, M., Sathi, S.N., Sorwar, G., Hossain, F., Ali, M.N.Y., Babu, H.M.H. (2015). An Efficient Design of a Reversible Fault Tolerant \(n\)-to-2\(^n\) Sequence Counter Using Nano Meter MOS Transistors. In: Tan, Y., Shi, Y., Buarque, F., Gelbukh, A., Das, S., Engelbrecht, A. (eds) Advances in Swarm and Computational Intelligence. ICSI 2015. Lecture Notes in Computer Science(), vol 9142. Springer, Cham. https://doi.org/10.1007/978-3-319-20469-7_48
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DOI: https://doi.org/10.1007/978-3-319-20469-7_48
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