Abstract
The on-going miniaturization of integrated circuit feature sizes has placed significant requirements on the on-chip power and ground distribution networks. Circuit integration densities rise with each nanoscale technology generation due to smaller devices and larger dies. The on-chip current densities and the total current also increase. Simultaneously, the higher switching speed of smaller transistors produces faster current transients in the power distribution network. Supplying high average currents and continuously increasing transient currents through the high impedance on-chip interconnects results in significant fluctuations of the power supply voltage in scaled CMOS technologies.
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References
K.T. Tang, E.G. Friedman, Simultaneous switching noise in on-chip CMOS power distribution networks. IEEE Trans. Very Large Scale Integr. (VLSI) Circuits 10(4), 487–493 (2002)
M. Benoit, S. Taylor, D. Overhauser, S. Rochel, Power distribution in high-performance design, in Proceedings of the IEEE International Symposium on Low Power Electronics and Design, pp. 274–278, Aug 1998
M. Popovich, E.G. Friedman, Decoupling capacitors for multi-voltage power distribution systems. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 14(3), 217–228 (2006)
M. Popovich, E.G. Friedman, Impedance Characteristics of Decoupling Capacitors in Multi-Power Distribution Systems, in Proceedings of the IEEE International Conference on Electronics, Circuits and Systems, pp. 160–163, Dec 2004
A.V. Mezhiba, E.G. Friedman, Power Distribution Networks in High Speed Integrated Circuits (Kluwer Academic, Norwell, 2004)
C.R. Paul, Introduction to Electromagnetic Compatibility (Wiley, New York, 1992)
H.B. Bakoglu, Circuit, Interconnections and Packaging for VLSI (Addison Wesley, Reading, 1990)
R.R. Tummala, E.J. Rymaszewski, A.G. Klopfenstein (eds.), Microelectronics Packaging Handbook (Chapman & Hall, New York, 1997)
D.J. Herrell, B. Beker, Modeling of power distribution systems for high-performance processors. IEEE Trans. Adv. Packag. 22(3), 240–248 (1999)
L.D. Smith, R.E. Anderson, D.W. Forehand, T.J. Pelc, T. Roy, Power distribution system design methodology and capacitor selection for modern CMOS technology. IEEE Trans. Adv. Packag. 22(3), 284–291 (1999)
A. Waizman, C.-Y. Chung, Resonant free power network design using extended adaptive voltage positioning (EAVP) methodology. IEEE Trans. Adv. Packag. 24(3), 236–244, (2001)
I.Novak, L.M. Noujeim, V. St Cyr, N. Biunno, A. Patel, G. Korony, A. Ritter, Distributed matched bypassing for board-level power distribution networks. IEEE Trans. Adv. Packag. 25(2), 230–242 (2002)
R. Panda, D. Blaauw, R. Chaudhry, V. Zolotov, B. Young, R. Ramaraju, Model and analysis for combined package and on-chip power grid simulation, in Proceedings of the IEEE International Symposium on Low Power Electronics and Design, pp. 179–184, Aug 2000
P.E. Gronowski, W.J. Bowhill, R.P. Preston, M.K. Gowan, R.L. Allmon, High-performance microprocessor design. IEEE J. Solid-State Circuits 33(5), 676–686 (1998)
R. Panda, S. Sundareswaran, D. Blaauw, On the interaction of power distribution network with substrate, in Proceedings of the IEEE International Symposium on Low Power Electronics and Design, pp. 388–393, Aug 2001
G.E.R. Lloyd, Early Greek Science: Thales to Aristotle (W. W. Norton, New York, 1974).
A.D. Moore, Electrostatics and Its Applications (Wiley, New York, 1973)
J.L. Heilborn, Electricity in the 17th & 18th Centuaries: A Study in Early Modern Physics (Dover, Mineola, 1999)
A. Guillemin, Electricity and Magnetism (Macmillam, London, 1891)
M. Faraday, Experimental Researches in Electricity (Dover, Mineola, 2004)
J.D. Cutnell, K.W. Johnson, Physics, 6th edn. (Wiley, Hoboken, 2003)
T.H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, 2nd edn. (Cambridge University Press, New York, 2004)
C.P. Yuan, T.N. Trick, A simple formula for the estimation of the capacitance of two-dimensional interconnects in VLSI circuits. IEEE Electron Device Lett. 3(12), 391–393 (1982)
N.P. van der Meijs, J.T. Fokkema, VLSI circuit reconstruction from mask topology. Integration 2(2), 85–119 (1984)
T. Roy, L. Smith, J. Prymak, ESR and ESL of ceramic capacitor applied to decoupling applications, in Proceedings of the IEEE Conference on Electrical Performance of Electronic Packaging, pp. 213–216, Oct 1998
D.A. Neamen, Semiconductor Physics and Devices: Basic Principles, 3rd edn. (McGraw-Hill, New York, 2002)
Power Distribution System (PDS) Design: Using Bypass/Decoupling Capacitors. http://direct.xilinx.com/bvdocs/appnotes/xapp623.pdf.
W. Becker, H. Smith, T. McNamara, P. Muench, J. Eckhardt, M. McAllister, G. Katopis, S. Richter, R. Frech, E. Klink, Mid-frequency simultaneous switching noise in computer systems, in Proceedings of the IEEE Electronic Components and Technology Conference, pp. 676–681, May 1997
T. Zhou, T. Strach, W.D. Becker, On chip circuit model for accurate mid-frequency simultaneous switching noise prediction, in Proceedings of the IEEE Conference on Electrical Performance of Electronic Packaging, pp. 275–278, Oct 2005
S. Bobba, T. Thorp, K. Aingaran, D. Liu, IC power distribution challenges, in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 643–650, Nov 2001
L. Smith, Simultaneous switching noise and power plane bounce for CMOS technology, in Proceedings of the IEEE Conference on Electrical Performance of Electronic Packaging, pp. 163–166, Oct 1999
F.Y. Yuan, Electromagnetic modeling and signal integrity simulations of power/ground networks in high speed digital packages and printed circuit boards, in Proceedings of the IEEE/ACM Design Automation Conference, pp. 421–426, June 1998
N. Na, J. Choi, S. Chun, M. Swaminathan, J. Srinivasan, Modeling and transient simulation of planes in electronic packages. IEEE Trans. Adv. Packag. 23(3), 340–352 (2000)
T.-G. Yew, Y.-L. Li, C.-Y. Chung, D.G. Figueroa, Design and performance evaluation of chip capacitors on microprocessor packaging, in Proceedings of the IEEE Conference on Electrical Performance of Electronic Packaging, pp. 175–178, Oct 1999
M. Xu, T.H. Hubing, J. Chen, T.P. Van Doren, J.L. Drewniak, R.E. DuBroff, Power-bus decoupling with embedded capacitance in printed circuit board design. IEEE Trans. Electromagn. Compat. 45(1), 22–30 (2003)
M.I. Montrose, Analysis on loop area trace radiated emissions from decoupling capacitor placement on printed circuit boards, in Proceedings of the IEEE International Symposium on Electromagnetic Compatibility, pp. 423–428, Aug 1999
P. Muthana, M. Swaminathan, E. Engin, P. Markondeya Raj, R. Tummala, Mid frequency decoupling using embedded decoupling capacitors, in Proceedings of the IEEE Conference on Electrical Performance of Electronic Packaging, pp. 271–274, Oct 2005
O.P. Mandhana, Design oriented analysis of package power distribution system considering target impedance for high performance microprocessors, in Proceedings of the IEEE Conference on Electrical Performance of Electronic Packaging, pp. 273–276, Oct 2001
L.D. Smith, D. Hockanson, Distributed SPICE circuit model for ceramic capacitors, in Proceedings of the IEEE Electronic Components and Technology Conference, pp. 523–528, May/June 2001
P. Larsson, Resonance and damping in CMOS circuits with on-chip decoupling capacitance. IEEE Trans. Circuits Syst. I: Fundam. Theory Appl. 45(8), 849–858 (1998)
L.D. Smith, R.E. Anderson, T. Roy, Chip-package resonance in core power supply structures for a high power microprocessor, in Proceedings of the ASME International Electronic Packaging Technical Conference and Exhibition, vol. 5, July 2001
C.R. Paul, Effectiveness of multiple decoupling capacitors. IEEE Trans. Electromag. Compat. 34(2), 130–133 (1992)
M. Popovich, E.G. Friedman, Decoupling capacitors for power distribution systems with multiple power supplies, in Proceedings of the IEEE EDS/CAS Activities in Western New York Conference, p. 9, Nov 2004
A. Waizman, C.-Y. Chung, Extended adaptive voltage positioning (EAVP), in Proceedings of the IEEE Conference on Electrical Performance of Electronic Packaging, pp. 65–68, Oct 2000
M. Sotman, M. Popovich, A. Kolodny, E.G. Friedman, Leveraging symbiotic on-die decoupling capacitance, in Proceedings of the IEEE Conference on Electrical Performance of Electronic Packaging, pp. 111–114, Oct 2005
H.H. Chen, J.S. Neely, Interconnect and circuit modeling techniques for full-chip power supply noise analysis. IEEE Trans. Compon. Packag. Manuf. Technol. Pt. B: Adv. Packag. 21(3), 209–215 (1998)
S. Bobba, I.N. Hajj, Input vector generation for maximum intrinsic decoupling capacitance of VLSI circuits, in Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 195–198, May 2001
R. Panda, S. Sundareswaran, D. Blaauw, Impact of low-impedance substrate on power supply integrity. IEEE Trans. Des. Test Comput. 20(3), 16–22, May/June 2003
G. Steele, D. Overhauser, S. Rochel, S.Z. Hussain, Full-chip verification methods for DSM power distribution systems, in Proceedings of the IEEE/ACM Design Automation Conference, pp. 744–749, June 1998
N.H. Pham, On-chip capacitor measurement for high performance microprocessor, in IEEE Topical Meeting on Electrical Performance of Electronic Packaging, pp. 65–68, Oct 1998.
H. Seidl et al., A fully integrated Al2O3 trench capacitor DRAM for Sub-100 nm technology, in Proceedings of the IEEE International Electron Devices Meeting, pp. 839–842, Dec 2002
K.V. Rao, M. Elahy, D.M. Bordelon, S.K. Banerjee, H.L. Tsai, W.F. Richardson, R.H. Womack, Trench capacitor design issues in VLSI DRAM cells, in Proceedings of the IEEE International Electron Devices Meeting, pp. 140–143, Dec 1986
W.J. Bowhill et al., Circuit implementation of a 300 MHz 64-bit second generation CMOS alpha CPU. Digit. Tech. J. 7(1), 100–118 (1995)
P. Larsson, Parasitic resistance in an MOS transistor used as on-chip decoupling capacitance. IEEE J. Solid-State Circuits 32(4), 574–576 (1997)
A. Hastings, The Art of Analog Layout (Prentice Hall, Upper Saddle River, 2001)
J.L. McCreary, Matching properties, and voltage and temperature dependence of MOS capacitors. IEEE J. Solid-State Circuits 16(6), 608–616 (1981)
R.T. Howe, C.G. Sodini, Microelectronics: An Integrated Approach (Prentice Hall, Upper Saddle River, 1996)
C.T. Black, K.W. Guarini, Y. Zhang, H. Kim, J. Benedict, E. Sikorski, I.V. Babich, K.R. Milkove, High-capacity, self-assembled metal-oxide-semiconductor decoupling capacitors. IEEE Electron Device Lett. 25(9), 622–624 (2004)
A.R. Alvarez, BiCMOS technology and applications (Kluwer Academic, Norwell, 1993)
A. Behr, M. Schneider, S. Filho, C. Montoro, Harmonic distortion caused by capacitors implemented with MOSFET gates. IEEE J. Solid-State Circuits 27(10), 1470–1475 (1992)
S. Rusu, J. Stinson, S. Tam, J. Leung, H. Muljono, B. Cherkauer, A 1.5-GHz 130-nm itanium 2 processor with 6-MB on-die L3 cache. IEEE J. Solid-State Circuits 38(11), 1887–1895 (2003)
Optimization of Metal-Metal Comb-Capacitors for RF Applications. http://www.oea.com/document/OptimizMetal.pdf
M.J. Deen, T.A. Fjeldly, CMOS RF Modeling, Characterization and Applications (World Scientific, River Edge, 2004)
R.K. Ulrich, L.W. Schaper, Integrated Passive Component Technology (Wiley-IEEE Press, New York, 2003)
S.B. Chen, C.H. Lai, A. Chin, J.C. Hsieh, J. Liu, High-density MIM capacitors using Al2O3 and AlTiO x dielectrics. IEEE Electron Device Lett. 23(4), 185–187 (2002)
M.Y. Yang, C.H. Huang, A. Chin, C. Zhu, M.F. Li, D.-L. Kwong, High-density MIM capacitors using AlTaO x dielectrics. IEEE Electron Device Lett. 24(5), 306–308 (2003)
X. Yu, C. Zhu, H. Hu, A. Chin, M.F. Li, B.J. Cho, D.-L. Kwong, P.D. Foo, M.B. Yu, A high-density MIM capacitor (13 fF/μm2) using ALD HfO2 dielectrics. IEEE Electron Device Lett. 24(2), 63–65 (2003)
H. Hu et al., High performance ALD HfO2–Al2O3 laminate MIM capacitors for RF and mixed signal IC applications, in Proceedings of the IEEE International Electron Devices Meeting, pp. 15.6.1–15.6.4, Dec 2003
S.-J. Ding et al., High-density MIM capacitor using ALD high-k HfO2 laminate dielectrics. IEEE Electron Device Lett. 24(12), 730–732 (2003)
S.-J. Kim, B.J. Cho, M.B. Yu, M.-F. Li, Y.-Z. Xiong, C. Zhu, A. Chin, D.-L. Kwong, Metal-insulator-metal RF bypass capacitor using niobium oxide (Nb2O5) with HfO2–Al2O3 barriers. IEEE Electron Device Lett. 26(9), 625–627 (2005)
Y.H. Wu, A. Chin, K.H. Shih, C.C. Wu, C.P. Liao, S.C. Pai, C.C. Chi, The fabrication of very high resistivity Si with low loss and cross talk. IEEE Electron Device Lett. 21(9), 442–444 (2000)
A. Kar-Roy, C. Hu, M. Racanelli, C.A. Compton, P. Kempf, G. Jolly, P.N. Sherman, J. Zheng, Z. Zhang, A. Yin, High density metal insulator metal capacitors using PECVD nitride for mixed signal and RF circuits, in Proceedings of the IEEE International Conference on Interconnect Technology, pp. 245–247, May 1999
J.A. Babcock, S.G. Balster, A. Pinto, C. Dirnecker, P. Steinmann, R. Jumpertz, B. El-Kareh, Analog characteristics of metal-insulator-metal capacitors using PECVD nitride dielectrics. IEEE Electron Device Lett. 22(5), 230–232 (2001)
P. Zurcher et al., Integration of thin film MIM capacitors and resistors into copper metallization based RF-CMOS and Bi-CMOS technologies, in Proceedings of the IEEE International Electron Devices Meeting, pp. 153–156, Dec 2000
C.H. Ng, K.W. Chew, J.X. Li, T.T. Tjoa, L.N. Goh, S.F. Chu, Characterization and comparison of two metal-insulator-metal capacitor schemes in 0.13 μm copper dual damascene metallization process for mixed-mode and RF applications, in Proceedings of the IEEE International Electron Devices Meeting, pp. 241–244, Dec 2002
N. Inoue, H. Ohtake, I. Kume, N. Furutake, T. Onodera, S. Saito, A. Tanabe, M. Tagami, M. Tada, Y. Hayashi, High performance high-k MIM capacitor with plug-in plate (PiP) for power delivery line of high-speed MPUs, in Proceedings of the IEEE International Interconnect Technology Conference, pp. 63–65, June 2006
T. Soorapanth, CMOS RF Filtering at GHz Frequency, Ph.D. Thesis, Stanford University, Stanford, 2002
Applications of Metal-Insulator-Metal (MIM) Capacitors, International SEMATECH, Technology Transfer No. 00083985A-ENG, Oct 2000.
O.E. Akcasu, High Capacitance Structures in a Semiconductor Device, U.S. Patent 5,208,725, 4 May 1993
B.B. Mandelbrot, The Fractal Geometry of Nature (Freeman, New York, 1983)
H. Samavati, A. Hajimiri, A.R. Shahani, G.N. Nasserbakht, and T.H. Lee, Fractal capacitors. IEEE J. Solid-State Circuits 33(12), 2035–2041 (1998)
R. Aparicio A. Hajimiri, Capacity limits and matching properties of integrated capacitors. IEEE J. Solid-State Circuits 37(3), 384–393 (2002)
A.C.C. Ng, M. Saran, Capacitor Structure for an Integrated Circuit, U.S. Patent 5,583,359, 10 Dec 1996
M. Popovich, E.G. Friedman, Decoupling capacitors for power distribution systems with multiple power supply voltages, in Proceedings of the IEEE International SOC Conference, pp. 331–334, Sept 2004
M. Popovich, E.G. Friedman, M. Sotman, A. Kolodny, R.M. Secareanu, Maximum effective distance of on-chip decoupling capacitors in power distribution grids, in Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration, pp. 173–179, Mar 2006
M. Ang, R. Salem, A. Taylor, An on-chip voltage regulator using switched decoupling capacitors, in Proceedings of the IEEE International Solid-State Circuits Conference, pp. 438–439, Feb 2000
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P.-Vaisband, I., Jakushokas, R., Popovich, M., Mezhiba, A.V., Köse, S., Friedman, E.G. (2016). Decoupling Capacitance. In: On-Chip Power Delivery and Management. Springer, Cham. https://doi.org/10.1007/978-3-319-29395-0_11
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