Abstract
In the era of BD explosion, poses significant challenges in the processing speed due to huge data volume and high dimension. To address this problem, we design a hardware implementation of K-means based on FPGA, named SAKMA, which can accelerate the whole algorithm in hardware and can be easily configured via parameters. What’s more, the accelerator makes the data size unlimited and can solve the problem about frequent off-chip memory access in a certain extent. Taking into account the hardware resource and power consumption, the SAKMA architecture adopts novel methods to accelerate the algorithm, including pipeline, tile technique, duplication parallelism, and hardware adder tree structures. In order to evaluate the performance of accelerator, we have constructed a real hardware prototype on Xilinx ZedBoard xc7z020clg484-1 FPGA. Experimental results demonstrate that the SAKMA architecture can achieve the speedup at 20.5 × with the affordable hardware cost.
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Acknowledgments
This work was supported by the National Science Foundation of China under grants (No. 61379040, No. 61272131, No. 61202053), Jiangsu Provincial Natural Science Foundation (No. SBK201240198), Open Project of State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences (No. CARCH201407), and the Strategic Priority Research Program of CAS (No. XDA06010403).
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Jia, F., Wang, C., Li, X., Zhou, X. (2015). SAKMA: Specialized FPGA-Based Accelerator Architecture for Data-Intensive K-Means Algorithms. In: Wang, G., Zomaya, A., Martinez, G., Li, K. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2015. Lecture Notes in Computer Science(), vol 9529. Springer, Cham. https://doi.org/10.1007/978-3-319-27122-4_8
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DOI: https://doi.org/10.1007/978-3-319-27122-4_8
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