Abstract
Side Channel Analysis (SCA), which has gained wide attentions during the past decade, has arisen as one of the most critical metrics for the cryptographic algorithm security evaluation. Typical SCA analyzes the data-dependent variations inspected from side channel leakages, such as power and electromagnetism (EM), to disclose intra secrets from cryptographic implementations on varying platforms, like microprocessor, FPGA, etc. Dual-rail Precharge Logic (DPL) has proven to be an effective logic-level countermeasure against classic correlation analysis by means of dual-rail compensation protocol. However, the DPL design is hard to be automated on FPGA, and the only published approach is subject to a simplified and partial AES core. In this paper, we present a novel implementation approach applied to a complete AES-128 crypto algorithm. This proposal bases on a partition mechanism which splits the whole algorithm to submodules and transform individuals to DPL format respectively. The main flavor lies within its highly symmetric dual-rail routing networks inside each block, which significantly reduces the routing bias between each routing pair in DPL. This paper describes the overall repair strategy and technical details. The experimental result shows a greatly elevated success rate during the routing repair phase, from lower than 60% to over 84% for Xilinx Virtex-5 FPGA in SASEBO-GII evaluation board.
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References
Kocher, P.C., Jaffe, J., Jun, B.: Differential Power Analysis. In: Wiener, M. (ed.) CRYPTO 1999. LNCS, vol. 1666, pp. 388–397. Springer, Heidelberg (1999)
Clarke, J.A., Constantinides, G.A., Cheung, P.Y.K.: On the feasibility of early routing capacitance estimation for FPGAs. In: FPL, pp. 234–239. IEEE Press, New York (2007)
He, W., Otero, A., de la Torre, E., et al.: Automatic generation of identical routing pairs for FPGA implemented DPL logic. In: International Conference on Reconfigurable Computing and FPGAs, pp. 1–6. IEEE Press, New York (2012)
Tiri, K., Verbauwhede, I.: A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation. In: Proceedings of the Conference on Design, Automation and Test in Europe, vol. 1, pp. 246–251. IEEE Computer Society (2004)
Tiri, K., Verbauwhede, I.: Synthesis of Secure FPGA Implementations. In: The Proceedings of the International Workshop on Logic and Synthesis (IWLS 2004), pp. 224–231 (June 2004)
Lavin, C., Padilla, M., Lundrigan, P., et al.: Rapid prototyping tools for FPGA designs: RapidSmith. In: International Conference on Field-Programmable Technology, pp. 353–356. IEEE Press, New York (2010)
Velegalati, R., Kaps, J.-P.: Improving Security of SDDL Designs Through Interleaved Placement on Xilinx FPGAs. In: 21st IEEE International Conference on Field Programmable Logic and Applications, Crete, Greece, pp. 506–511. IEEE Press, New York (2011)
Shah, S., Velegalati, R., Kaps, J.-P., Hwang, D.: Investigation of DPA Resistance of Block RAMs in Cryptographic Implementations on FPGAs. In: Prasanna, V.K., Becker, J., Cumplido, R. (eds.) ReConFig, pp. 274–279. IEEE Computer Society (2010)
Tiri, K., Verbauwhede, I.: Secure Logic Synthesis. In: Becker, J., Platzner, M., Vernalde, S. (eds.) FPL 2004. LNCS, vol. 3203, pp. 1052–1056. Springer, Heidelberg (2004)
He, W., de la Torre, E., Riesgo, T.: An interleaved EPE-immune PA-DPL structure for resisting concentrated EM side channel attacks on FPGA implementation. In: Schindler, W., Huss, S.A. (eds.) COSADE 2012. LNCS, vol. 7275, pp. 39–53. Springer, Heidelberg (2012)
Lavin, C., Padilla, M., Lamprecht, J., et al.: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs. In: 21st IEEE International Conference on Field Programmable Logic and Applications, pp. 349–355. IEEE Press, New York (2011)
Lavin, C., Padilla, M., Lamprecht, J., et al.: HMFlow: Accelerating FPGA Compilation with Hard Macros for Rapid Prototyping. In: IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, pp. 117–124. IEEE Press, New York (2011)
RAPIDSMITH: A Library for Low-level Manipulation of Partially Placed-and-Routed FPGA Designs. Technical Report and Documentation (November 2013), http://rapidsmith.sourceforge.net/doc/TechReportAndDocumentation.pdf
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Tu, C., He, W., Gao, N., de la Torre, E., Liu, Z., Liu, L. (2014). A Progressive Dual-Rail Routing Repair Approach for FPGA Implementation of Crypto Algorithm. In: Huang, X., Zhou, J. (eds) Information Security Practice and Experience. ISPEC 2014. Lecture Notes in Computer Science, vol 8434. Springer, Cham. https://doi.org/10.1007/978-3-319-06320-1_17
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DOI: https://doi.org/10.1007/978-3-319-06320-1_17
Publisher Name: Springer, Cham
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