Abstract
This paper introduces a computer architecture, where part of the instruction set architecture (ISA) is implemented on small highly-integrated field-programmable gate arrays (FPGAs). Small FPGAs inside a general-purpose processor (CPU) can be used effectively to implement custom or standardised instructions. Our proposed architecture directly address related challenges for high-end CPUs, where such highly-integrated FPGAs would have the highest impact, such as on main memory bandwidth. This also enables software-transparent context-switching. The simulation-based evaluation of a dynamically reconfigurable core shows promising results approaching the performance of an equivalent core with all enabled instructions. Finally, the feasibility of adopting the proposed architecture in today’s CPUs is studied through the prototyping of fast-reconfigurable FPGAs and profiling the miss behaviour of opcodes.
The first author is now with Huawei Technologies R &D (UK) Limited.
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Notes
- 1.
Source code available: https://github.com/pphilippos/fpga-ext-arch.
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Acknowledgement
We would like to thank Anuj Vaishnav for his feedback on an earlier version. The second author mainly contributed with the Sect. 5.1.
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Papaphilippou, P., Shah, M. (2022). FPGA-Extended General Purpose Computer Architecture. In: Gan, L., Wang, Y., Xue, W., Chau, T. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2022. Lecture Notes in Computer Science, vol 13569. Springer, Cham. https://doi.org/10.1007/978-3-031-19983-7_7
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