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Secure and Efficient Software Masking on Superscalar Pipelined Processors

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Advances in Cryptology – ASIACRYPT 2021 (ASIACRYPT 2021)

Part of the book series: Lecture Notes in Computer Science ((LNSC,volume 13091))

Abstract

Physical side-channel attacks like power analysis pose a serious threat to cryptographic devices in real-world applications. Consequently, devices implement algorithmic countermeasures like masking. In the past, works on the design and verification of masked software implementations have mostly focused on simple microprocessors that find usage on smart cards. However, many other applications such as in the automotive industry require side-channel protected cryptographic computations on much more powerful CPUs. In such situations, the security loss due to complex architectural side-effects, the corresponding performance degradation, as well as discussions of suitable probing models and verification techniques are still vastly unexplored research questions.

We answer these questions and perform a comprehensive analysis of more complex processor architectures in the context of masking-related side effects. First, we analyze the RISC-V SweRV core—featuring a 9-stage pipeline, two execution units, and load/store buffers—and point out a significant gap between security in a simple software probing model and practical security on such CPUs. More concretely, we show that architectural side effects of complex CPU architectures can significantly reduce the protection order of masked software, both via formal analysis in the hardware probing model, as well as empirically via gate-level timing simulations. We then discuss the options of fixing these problems in hardware or leaving them as constraints to software. Based on these software constraints, we formulate general rules for the design of masked software on more complex CPUs. Finally, we compare several implementation strategies for masking schemes and present in a case study that designing secure masked software for complex CPUs is still possible with overhead as low as 13%.

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Notes

  1. 1.

    https://github.com/barbara-gigerl/sw-masking-swerv.

  2. 2.

    https://github.com/chipsalliance/Cores-SweRV.

  3. 3.

    Even if the selector signals were stable, e.g. by calculating and buffering them in the previous clock cycle, there is still no guarantee that this signal arrives at all multiplexers in stable condition in the next clock cycle due to different wire lengths.

  4. 4.

    https://github.com/RTimothyEdwards/qflow/tree/master/tech.

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Acknowledgements

This work was supported by the TU Graz LEAD project “Dependable Internet of Things in Adverse Environments”, and the Austrian Research Promotion Agency (FFG) via the K-project DeSSnet, which is funded in the context of COMET – Competence Centers for Excellent Technologies by BMVIT, BMWFW, Styria and Carinthia, and via the FERMION project (grant nr 867542).

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Authors and Affiliations

  1. Graz University of Technology, Graz, Austria

    Barbara Gigerl, Robert Primas & Stefan Mangard

  2. Lamarr Security Research, Graz, Austria

    Stefan Mangard

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  1. Barbara Gigerl
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  2. Robert Primas
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  3. Stefan Mangard
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Corresponding authors

Correspondence to Barbara Gigerl , Robert Primas or Stefan Mangard .

Editor information

Editors and Affiliations

  1. NTT Corporation, Tokyo, Japan

    Mehdi Tibouchi

  2. Nanyang Technological University, Singapore, Singapore

    Huaxiong Wang

Appendices

Appendix A

See Fig. 5.

Fig. 5.
figure 5

Comparison between serial and parallel DOM Keccak S-box

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Appendix B

See Table 2.

Table 2. Circuit size of the SweRV core (256 byte of data memory, 2 KB of instruction memory/cache) before and after optimization (Removal of unused instruction memory logic)
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Gigerl, B., Primas, R., Mangard, S. (2021). Secure and Efficient Software Masking on Superscalar Pipelined Processors. In: Tibouchi, M., Wang, H. (eds) Advances in Cryptology – ASIACRYPT 2021. ASIACRYPT 2021. Lecture Notes in Computer Science(), vol 13091. Springer, Cham. https://doi.org/10.1007/978-3-030-92075-3_1

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