Abstract
Recently the ForkAES construction was proposed by Andreeva et al. for efficiently performing authenticated encryption of very short messages on next generation IoT devices. The ForkAES tweakable block cipher uses around one and a half AES encryption calls to produce a pair of ciphertexts for any given plaintext. However the only downside of the construction is that it needs to store an extra state of 128 bits in addition with the storage elements required to perform AES encryption. Thus a hardware implementation of ForkAES would require additional circuit area to accommodate the extra state.
In this paper, we first show that it is possible to implement ForkAES without any additional storage elements other than those required to implement AES, if the AES circuit can additionally perform decryption. Such an implementation naturally requires more clock cycles to perform ForkAES operations. We extend the recently proposed Atomic AES v2.0 architecture to realize ForkAES and compare the area-latency trade-offs incurred with and without an additional storage. The area of the most compact ForkAES design takes about 1.2 times that of AES.
In the second part of the paper we look at another important parameter of lightweight efficiency, i.e. energy. It is well known that round based constructions for AES are the most energy efficient ones. We extend the so-called “\(S_3K_2\)” construction of Banik et al. (IEEE HOST 17) to realize ForkAES in an energy-preserving manner, and compare the effects of some design choices. The energy consumption of our best ForkAES design takes about 2 times that of AES. From lightweight design perspective, our results hence demonstrate that although ForkAES lives up to its promise (of being roughly 1.5 times that of AES) in terms of its area, the same does not hold for its energy consumption.
The source code for our implementations are provided at [1].
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Notes
- 1.
More precisely, the value is loaded into \(\mathsf {Register_{St}}\) during the rising edge that marks the end of cycle 0, hence the value itself becomes available at the output of the register at cycle 1. We rather say the value is loaded into the register at clock cycle 0.
- 2.
Note that \(\textsf {SB} ^{-1}(\textsf {SR} ^{-1}(x)) = \textsf {SR} ^{-1}(\textsf {SB} ^{-1}(x))\) for all x.
- 3.
This metric omits the additional higher-level circuitry such as control blocks to handle multiple associated data and message blocks in SAEF and PAEF, as we only focus on the ForkAES implementation.
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The authors are supported by the Swiss National Science Foundation (SNSF) through the Ambizione Grant PZ00P2_179921.
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Balli, F., Banik, S. (2019). Exploring Lightweight Efficiency of ForkAES. In: Hao, F., Ruj, S., Sen Gupta, S. (eds) Progress in Cryptology – INDOCRYPT 2019. INDOCRYPT 2019. Lecture Notes in Computer Science(), vol 11898. Springer, Cham. https://doi.org/10.1007/978-3-030-35423-7_26
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