Abstract
This chapter investigates the architectural design of a 3D die-stacked Graphics Processing Unit. The investigation includes a discussion of the design space of the system as well as some empirical results that quantify the expected performance gain of such a system. Also, the chapter discusses the cost, power and thermal aspects of the proposed designs.
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Acknowledgment
The work appeared in this chapter was supported in part by NSF grants 0903432; 0702617.
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Al Maashri, A., Sun, G., Dong, X., Xie, Y., Vijaykrishnan, N. (2011). Influence of Stacked 3D Memory/Cache Architectures on GPUs. In: Sheibanyrad, A., Pétrot, F., Jantsch, A. (eds) 3D Integration for NoC-based SoC Architectures. Integrated Circuits and Systems. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-7618-5_11
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