Polymorphic Instruction Set Computers

1. S. Vassiliadis, B. Blaner, and R. J. Eickemeyer, SCISM: A scalable compound instruction set machine. IBM J. Res. Develop. Vol. 38, No. 2, January 1994, pp. 59–78.

   Google Scholar 

2. G. M. Amdahl, Validity of the single processor approach to achieving large scale computing capabilities, in Proc. AFIPS 1967 Spring Joint Computer Conference, 1967, pp. 483–485.

   Google Scholar 

3. D. A. Patterson and D. R. Ditzel, The case for the reduced instruction set computer, SIGARCH Comput. Archit. News, Vol. 8, No. 6, Oct 1980, pp. 25–33.

   Article  Google Scholar 

4. D. Bhandarkar and D. W. Clark. Performance from Architecture: Comparing a RISC and a CISC with Similar Hardware Organization. Communications of the ACM, Sep 1991, pp. 310–319.

   Google Scholar 

5. G. Roelofs. PNG: The Definitive Guide. O’Reilly and Associates, 1999.

   Google Scholar 

6. E. A. Hakkennes and S. Vassiliadis, Hardwired Paeth codec for portable network graphics (PNG), Euromicro 99, September 1999, pp. 318–325,

   Google Scholar 

7. S. Hauck, T. Fry, M. Hosler, and J. Kao, The Chimaera Reconfigurable Functional Unit, in Proc. IEEE Symp. on Field-Programmable Custom Computing Machines, 1997, pp. 87–96.

   Google Scholar 

8. A. L. Rosa, L. Lavagno, and C. Passerone, Hardware/Software Design Space Exploration for a Reconfigurable Processor, in Proc. Design, Automation and Test in Europe 2003 (DATE 2003), 2003, pp. 570–575.

   Google Scholar 

9. S. Vassiliadis, S. Wong, and S. Cotofana, “Microcode Processing: Positioning and Directions,” IEEE Micro, vol. 23, no. 4, pp. 21–30, July/August 2003.

   Article  Google Scholar 

10. S. Vassiliadis, G. Gaydadjiev, K. Bertels, and E. Moscu Panainte, “The Molen Programming Paradigm,” in Proceedings of the Third International Workshop on Systems, Architectures, Modeling, and Simulation, Samos, Greece, July 2003, pp. 1–7.

    Google Scholar 

11. S. Vassiliadis, S. Wong, and S. Cotofana, “The MOLEN ρ μ-Coded Processor,” in 11th International Conference on Field Programmable Logic and Applications (FPL), vol. 2147. 1em plus 0.5em minus 0.4em Belfast, UK: Springer-Verlag Lecture Notes in Computer Science (LNCS), Aug 2001, pp. 275–285.

    Google Scholar 

12. S. Vassiliadis, S. Wong, G. N. Gaydadjiev, K. Bertels, G. Kuzmanov, and E. M. Panainte, “The Molen Polymorphic Processor,” IEEE Transactions on Computers, vol. 53, pp. 1363–1375, November 2004.

    Article  Google Scholar 

13. F. Campi, M. Toma, A. Lodi, A. Cappelli, R. Canegallo, and R. Guerrieri, “A VLIW Processor with Reconfigurable Instruction Set for Embedded Applications,” in In ISSCC Digest of Technical Papers, Feb 2003, pp. 250–251.

    Google Scholar 

14. A. Ye, N. Shenoy, and P. Banerjee, “A C Compiler for a Processor with a Reconfigurable Functional Unit,” in ACM/SIGDA Symposium on FPGAs, Montery, California, USA, 2000, pp. 95–100.

    Google Scholar 

15. A. Padegs, B. Moore, R. Smith, and W. Buchholz, “The IBM System/370 Vector Architecture: Design Considerations,” IEEE Transactions on Computers, vol. 37, pp. 509–520, 1988.

    Google Scholar 

16. W. Buchholz, “The IBM System/370 Vector Architecture,” IBM Systems Journal, vol. 25, no. 1, pp. 51–62, 1986.

    Article  MathSciNet  Google Scholar 

17. M. Moudgill and S. Vassiliadis, “Precise Interrupts,” IEEE Micro, vol. 16, no. 1, pp. 58–67, January 1996.

    Article  Google Scholar 

18. E. Moscu-Panainte, K. Bertels, and S. Vassiliadis, “Compiling for the Molen Programming Paradigm,” in 13th International Conference on Field Programmable Logic and Applications (FPL), vol. 2778. Lisbon, Portugal: Springer-Verlag Lecture Notes in Computer Science (LNCS), Sep 2003, pp. 900–910.

    Google Scholar 

19. http://suif.stanford.edu/suif/suif2.

    Google Scholar 

20. http://www.eecs.hardvard.edu/hube/research/machsuif.html.

    Google Scholar 

21. M. Gokhale and J. Stone, “Napa C: Compiling for a Hybrid RISC/FPGA Architecture,” in Proc. IEEE Symp. on Field-Programmable Custom Computing Machines, Napa, California, April 1998, pp. 126–135.

    Google Scholar 

22. E. Moscu-Panainte, K. Bertels, and S. Vassiliadis, Compiler-driven FPGA-area Allocation for Reconfigurable Computing, in Proceedings of Design, Automation and Test in Europe 2006 (DATE 06), March 2006.

    Google Scholar 

23. A. Turjan, T. Stefanov, B. Kienhuis, and E. Deprettere, “The Compaan Tool Chain: Converting Matlab into Process Networks,” in Designer’s Forum of DATE 2002, pp. 258–264, 2003.

    Google Scholar 

24. B. Kienhuis, E. Rypkema, and E. Deprettere, “Compaan: deriving process networks from Matlab for embedded signal processing architectures,” in Proceedings of the 8th International Workshop on Hardware/Software Codesign (CODES), pp. 13–17, May 2000.

    Google Scholar 

25. C. Zissulescu, T. Stefanov, B. Kienhuis, and E. Deprettere, “Laura: Leiden Architecture Research and Exploration Tool,” in 13th International Conference on Field Programmable Logic and Applications (FPL 2003), pp. 911–920, LNCS 2778, September 2003.

    Google Scholar 

26. G. Kahn, “The Semantics of a Simple Language for Parallel Programming,” in Proceedings of the IFIP Congress ’74, pp. 471–475, August 5-10 1974.

    MathSciNet  Google Scholar 

27. S. Vassiliadis, E. Hakkennes, S. Wong, and G. Pechanek, “The Sum-of-Absolute-Difference Motion Estimation Accelerator,” in Proceedings of the 24th Euromicro Conference, August 1998, pp. 559–566.

    Google Scholar 

Download references