Abstract
In this paper, we present a methodology for mapping an Embedded Signal Processing (ESP) application onto HPC platforms such that the throughput performance is maximized. Previous approaches used a linear pipelined execution model which restrict the mapping choices. We show that the “optimal” solution obtained under that model can be improved, using the proposed execution model. Based on the new model, a three-step task mapping methodology is developed. The methodology is demonstrated by designing Software Task Pipelines for modern radar and sonar signal processing applications. Experimental results show improved performance using our approach over those obtained by previous approaches.
Work supported in part by DARPA Embedded Systems Program under contract no. DABT63-95-C-0092 monitored by Fort Hauchuca.
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© 1998 Springer-Verlag Berlin Heidelberg
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Lee, M., Liu, W., Prasanna, V.K. (1998). A mapping methodology for designing software task pipelines for embedded signal processing. In: Rolim, J. (eds) Parallel and Distributed Processing. IPPS 1998. Lecture Notes in Computer Science, vol 1388. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-64359-1_759
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DOI: https://doi.org/10.1007/3-540-64359-1_759
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