Abstract
A new parallel processor structure for Givens QR-decomposition intended for the FPGA implementation is presented. The structure is derived using method of mapping regular algorithms using affine transformations of the algorithm graph. The method supports pipelined processor unit design, and provides efficient hardware utilization. An example of the implementation of this structure in the Xilinx Virtex FPGA devices is presented.
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Sergyienko, A., Maslennikov, O. (2002). Implementation of Givens QR-Decomposition in FPGA. In: Wyrzykowski, R., Dongarra, J., Paprzycki, M., Waśniewski, J. (eds) Parallel Processing and Applied Mathematics. PPAM 2001. Lecture Notes in Computer Science, vol 2328. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-48086-2_50
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DOI: https://doi.org/10.1007/3-540-48086-2_50
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