[go: up one dir, main page]
More Web Proxy on the site http://driver.im/
Skip to main content

Partial Evaluation of Hardware

  • Conference paper
Partial Evaluation (DIKU 1998)

Part of the book series: Lecture Notes in Computer Science ((LNAI,volume 1706))

Included in the following conference series:

  • 687 Accesses

Abstract

The preliminary results of dynamically specialising Xilinx XC6200 FPGA circuits using partial evaluation are presented. This method provides a systematic way to manage to complexity of dynamic reconfiguration in the special case where a general circuit is specialised with respect to one input which changes more slowly than the other inputs.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Similar content being viewed by others

References

  1. T. Kean, B. New, B. Slous. A Multiplier for the XC6200. Sixth International Workshop on Field Programmable Logic and Applications. Darmstadt, 1996.

    Google Scholar 

  2. H. T. Kung. Why Systolic Architectures. IEEE Computers. January 1982.

    Google Scholar 

  3. National Bureau of Standards. Data Encryption Standard (DES), Technical Report, National Bureau of Standards (USA), Federal Information Processing Standards, Publication 46, National Technical Information Services, Springfield, Virginia, April 1997.

    Google Scholar 

  4. N. D. Jones, C. K. Gomard, and P. Sestoft, Partial Evaluation and Automatic Program Generation, Prentice-Hall, 1993.

    Google Scholar 

  5. Jason Leonard and William H. Mangione-Smith. A Case Study of Partially Evaluated Hardware Circuits: Key-Specific DES. FPL’97. 1997.

    Google Scholar 

  6. M. Sheeran, G. Jones. Circuit Design in Ruby. Formal Methods for VLSI Design, J. Stanstrup, North Holland, 1992.

    MATH  Google Scholar 

  7. Satnam Singh and Pierre Bellec. Virtual Hardware for Graphics Applications using FPGAs. FCCM’94. IEEE Computer Society, 1994.

    Google Scholar 

  8. Satnam Singh. Architectural Descriptions for FPGA Circuits. FCCM’95. IEEE Computer Society. 1995.

    Google Scholar 

  9. Michael J. Wirthlin and Brad L. Hutchings. Improving Functional Density Through Run-Time Constant Propagation. FPGA’97. 1997.

    Google Scholar 

  10. Xilinx. XC6200 FPGA Family Data Sheet. Xilinx Inc. 1995.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 1999 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Singh, S., McKay, N. (1999). Partial Evaluation of Hardware. In: Hatcliff, J., Mogensen, T.Æ., Thiemann, P. (eds) Partial Evaluation. DIKU 1998. Lecture Notes in Computer Science, vol 1706. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-47018-2_8

Download citation

  • DOI: https://doi.org/10.1007/3-540-47018-2_8

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-66710-0

  • Online ISBN: 978-3-540-47018-2

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics