Abstract
In this research a refined interface between high-level design languages and hardware verification platforms is developed. Our interface methodology is demonstrated through the integration of a communication system design, written in C and SystemC, with a multi-FPGA logic emulator from Ikos Systems. We show that as designs are refined from a high-level to a gate-level representation, our methodology improves verification performance while maintaining verification fidelity across a range of abstraction levels.
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© 2002 Springer-Verlag Berlin Heidelberg
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Ramaswamy, R., Tessier, R. (2002). The Integration of SystemC and Hardware-Assisted Verification. In: Glesner, M., Zipf, P., Renovell, M. (eds) Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream. FPL 2002. Lecture Notes in Computer Science, vol 2438. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-46117-5_103
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DOI: https://doi.org/10.1007/3-540-46117-5_103
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