Abstract
In this paper we present an algorithm to contrast state explosion when using Explicit State Space Exploration to verify protocols. We show experimentally that protocols exhibit transition locality.
We present a verification algorithm that exploits transition locality as well as an implementation of it within the Murϕ verifier.
Our algorithm is compatible with all Breadth First (BF) optimization techniques present in the Murϕ verifier and it is by no means a substitute for any of them. In fact, since our algorithm trades space with time, it is typically most useful when one runs out of memory and has already used all other state reduction techniques present in the Murϕ verifier.
Our experimental results show that using our approach we can typically save more than 40% of RAM with an average time penalty of about 50% when using (Murϕ) bit compression and 100% when using bit compression and hash compaction.
This research has been partially supported by MURST project TOSCA
Chapter PDF
We’re sorry, something doesn't seem to be working properly.
Please try refreshing the page. If that doesn't work, please contact support so we can address the problem.
Keywords
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
References
R. Bryant. Graph-based algorithms for boolean function manipulation. IEEE Trans. on Computers, C-35(8), Aug 1986.
J. R. Burch, E. M. Clarke, K. L. McMillan, D. L. Dill, and L. J. Hwang. Symbolic model checking: 1020 states and beyond. Information and Computation, (98), 1992.
D. L. Dill, A. J. Drexler, A. J. Hu, and C. H. Yang. Protocol verification as a hardware design aid. In IEEE International Conference on Computer Design: VLSI in Computers and Processors, pages 522–5, 1992.
G. J. Holzmann. The spin model checker. IEEE Trans. on Software Engineering, 23(5):279–295, May 1997.
G. J. Holzmann. An analysis of bitstate hashing. Formal Methods in Systems Design, 1998.
A. J. Hu, G. York, and D. L. Dill. New techniques for efficient verification with implicitily conjoined bdds. In 31st IEEE Design Automation Conference, pages 276–282, 1994.
C. N. Ip and D. L. Dill. Better verification through symmetry. In 11th International Conference on Computer Hardware Description Languages and their Applications, pages 97–111, 1993.
C. N. Ip and D. L. Dill. Efficient verification of symmetric concurrent systems. In IEEE International Conference on Computer Design: VLSI in Computers and Processors, pages 230–234, 1993.
Heh-Tyan Liaw and Chen-Shang Lin. On the obdd-representation of general boolean functions. IEEE Trans. on Computers, C-41(6), June 1992.
A. Papoulis. Probability, Random Variables and Stochastic Processes. McGraw-Hill Series in System Sciences, 1965.
D. A. Patterson and J. L. Hennessy. Computer Architecture A Quantitative Approach. Morgan Kaufmann, 1996.
R. K. Ranjan, J. V. Sanghavi, R. K. Brayton, and A. Sangiovanni-Vincentelli. Binary decision diagrams on network of workstations. In IEEE International Conference on Computer Design, pages 358–364, 1996.
J. V. Sanghavi, R. K. Ranjan, R. K. Brayton, and A. Sangiovanni-Vincentelli. High performance bdd package by exploiting memory hierarchy. In 33rd IEEE Design Automation Conference, 1996.
url: http://netlib.bell-labs.com/netlib/spin/whatispin.html.
U. Stern and D. Dill. Parallelizing the murϕ verifier. In Proc. 9th Int. Conference on Computer Aided Verification, volume 1254, pages 256–267, Haifa, Israel, 1997. LNCS, Springer.
U. Stern and D. Dill. Using magnetic disk instead of main memory in the murϕ verifier. In Proc. 10th Int. Conference on Computer Aided Verification, volume 1427, pages 172–183, Vancouver, BC, Canada, 1998. LNCS, Springer.
U. Stern and D. L. Dill. Improved probabilistic verification by hash compaction. In IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods, pages 206–224, 1995.
U. Stern and D. L. Dill. A new scheme for memory-efficient probabilistic verification. In IFIP TC6/WG6.1 Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols, and Protocol Specification, Testing, and Verification, 1996.
T. Stornetta and F. Brewer. Implementation of an efficient parallel bdd package. In 33rd IEEE Design Automation Conference, pages 641–644, 1996.
Pierre Wolper and Dennis Leroy. Reliable hashing without collision detection. In Proc. 5th Int. Conference on Computer Aided Verification, pages 59–70, Elounda, Greece, 1993.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2001 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Tronci, E., Della Penna, G., Intrigila, B., Zilli, M.V. (2001). Exploiting Transition Locality in Automatic Verification. In: Margaria, T., Melham, T. (eds) Correct Hardware Design and Verification Methods. CHARME 2001. Lecture Notes in Computer Science, vol 2144. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44798-9_22
Download citation
DOI: https://doi.org/10.1007/3-540-44798-9_22
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-42541-0
Online ISBN: 978-3-540-44798-6
eBook Packages: Springer Book Archive