Abstract
The paper describes the implementation of a systolic array for a multilayer perceptron on different FPGA architectures with a hardware-friendly learning algorithm: Pipelined On-line Backpropagation. By exploiting the embedded memories of certain families alongside the projection used in the systolic architecture, we can implement very large interconnection layers. These physical and architectural features — together with the combination of FPGA reconfiguration properties with a design flow based on generic VHDL — permit us to create an easy, flexible and fast method of designing a complete ANN on a single FPGA. The result offers a high degree of parallelism and fast performance.
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© 2000 Springer-Verlag Berlin Heidelberg
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Gadea, R., Herrero, V., Sebastia, A., Mocholí, A. (2000). The Role of the Embedded Memories in the Implementation of Artificial Neural Networks. In: Hartenstein, R.W., Grünbacher, H. (eds) Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing. FPL 2000. Lecture Notes in Computer Science, vol 1896. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44614-1_85
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DOI: https://doi.org/10.1007/3-540-44614-1_85
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