Abstract
A MIMD type highly parallel processor comprising 4096 processing elements (PEs) with a nearest neighbor mesh connection is studied. The system realizes more than 100MB/S initial data transfer capability by multi-layering PE arrays, transmitting data from each upper layer PE to dependent lower layer PEs simultaneously. This configuration reduces the maximum internode distance and the inter-PE data transfer delay by relaying inter-PE data via upper layer PEs. High speed inter-PE synchronizations, for instance, synchronization of all PEs and local synchronization within any layer, have been realized (less than one microsecond for all PEs). A small scale system with 256 PEs is now under fabrication. Each PE consists of a 16-bit micro-processor, DRAMs and two newly developed types of LSIs. The size of a PE is 9cm × 6cm × 3cm.
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© 1986 Springer-Verlag Berlin Heidelberg
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Momoi, S., Shimada, S., Kobayashi, M., Ishikawa, T. (1986). Hierarchical array processor system (HAP). In: Händler, W., Haupt, D., Jeltsch, R., Juling, W., Lange, O. (eds) CONPAR 86. CONPAR 1986. Lecture Notes in Computer Science, vol 237. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-16811-7_185
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DOI: https://doi.org/10.1007/3-540-16811-7_185
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