Abstract
This paper presents a hardware implementation of a dual mode Tate pairing/elliptic curve processor over fields of characteristic 2. The architecture can be reconfigured for different underlying field sizes and hence can support different security levels. The processor also performs elliptic curve point scalar multiplication. The performance of the architecture implemented on an FPGA is evaluated for various security levels.
This is a preview of subscription content, log in via an institution to check access.
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Dutta, R., Barua, R., Sarkar, P.: Pairing-Based Cryptographic Protocols: A Survey. Cryptology ePrint Archive, Report 064/2004 (2004)
Boneh, D., Franklin, M.: Identity Based Encryption from the Weil Pairing. SIAM J. of Computing 32(3), 586–615 (2003)
Zhao, M., Smith, S.W., Nicol, D.M.: Aggregated Path Authentication for Efficient BGP Security. In: Proc. 12th ACM Conference on Computer and Communications Security, pp. 128–138 (November 2005)
Barreto, P.S.L.M., Kim, H.Y., Lynn, B., Scott, M.: Efficient Algorithms for Pairing-Based Cryptosystems. In: Yung, M. (ed.) CRYPTO 2002. LNCS, vol. 2442, pp. 354–368. Springer, Heidelberg (2002)
Galbraith, S.D., Harrison, K., Soldera, D.: Implementing the Tate Pairing. In: Proc. Fifth Algorithmic Number Theory Symp (ANTS-V), pp. 324–337 (2002)
Duursma, I., Lee, H.-S.: Tate Pairing Implementation for Hyperelliptic Curves y 2 = x p − x + d. In: Laih, C.-S. (ed.) ASIACRYPT 2003. LNCS, vol. 2894, pp. 111–123. Springer, Heidelberg (2003)
Barreto, P.S.L.M., Galbraith, S., O’hEigeartaigh, C., Scott, M.: Efficient Pairing Computation on Supersingular Abelian Varieties. Cryptology ePrint Archive, Report 375/2004 (2004)
Celoxica RC 2000 (2000), http://www.celoxica.com/products/rc2000/default.asp
Kerins, T., Marnane, W.P., Popovici, E.M., Barreto, P.S.L.M.: Hardware Accelerators for Pairing Based Cryptosystems. In: IEE Proceedings on Information Security, vol. 155(1), pp. 47–56 (October 2005)
Ronan, R., O’hEigeartaigh, C., Murphy, C., Scott, M., Kerins, T., Marnane, W.P.: A Dedicated Processor for the eta Pairing. Cryptology ePrint Archive, Report 330/2005 (2005)
Knuth, D.: The Art of Computer Programming: Seminumerical Algorithms, 2nd edn., vol. 2. Addison-Wesley, Reading (1981)
Song, L., Parhi, K.: Low Energy Digit-Serial/Parallel Finite Field Multipliers. Kulwer Journal of VLSI Signal Processing Systems 19(2), 149–166 (1998)
Shantz, S.C.: From Euclid’s GCD to Montgomery Multiplication to the Great Divide. TR-2001-95, Technical Report, Sun Microsystems (2001)
Karatsuba, A., Ofman, Y.: Multiplication on Many-Digital Numbers by Automatic Computers. Translation in Physics-Doklady 7, 595–596 (1963)
Keller, M., Kerins, T., Marnane, W.: FPGA Implementation of a GF(24m) Multiplier for use in Pairing Based Cryptosystems. In: Proc. International Conference on Field Programmable Logic and Applications 2005, pp. 594–597 (August 2005)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2006 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Keller, M., Kerins, T., Crowe, F., Marnane, W. (2006). FPGA Implementation of a GF(2m) Tate Pairing Architecture. In: Bertels, K., Cardoso, J.M.P., Vassiliadis, S. (eds) Reconfigurable Computing: Architectures and Applications. ARC 2006. Lecture Notes in Computer Science, vol 3985. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11802839_44
Download citation
DOI: https://doi.org/10.1007/11802839_44
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-36708-6
Online ISBN: 978-3-540-36863-2
eBook Packages: Computer ScienceComputer Science (R0)