[go: up one dir, main page]
More Web Proxy on the site http://driver.im/
Skip to main content
Springer Nature Link
Log in

Power Estimation of CMOS Circuits by Neural Network Macromodel

  • Conference paper
Advances in Neural Networks - ISNN 2006 (ISNN 2006)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 3973))

Included in the following conference series:

  • 1679 Accesses

Abstract

Neural network is employed to construct the power macromodel of complementary metal-oxide-semiconductor (CMOS) integrated circuits. In contrast to previous modeling approaches, it does not require empirically constructed specialized analytical equations for the power macromodel, and obtained statistics of a circuit’s primary outputs simultaneously. It is suitable for power estimation in core-based systems-on-chips (SoCs) with pre-designed blocks. In experiments with the ISCAS-85 circuits, the average absolute relative error of the macromodel was below 5.0% for not only the average power dissipation, but also the maximum power dissipation.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Similar content being viewed by others

References

  1. Najm, F.N.: A Survey of Power Estimation Techniques in VLSI Circuits. IEEE Trans. VLSI Systems 2(4), 446–455 (1994)

    Article  Google Scholar 

  2. Liu, X., Papaefthymiou, M.C.: A Markov Chain Sequence Generator for Power Macromodeling. IEEE Trans. CAD of Integrated Circuits and Systems 23(7), 1048–1062 (2004)

    Article  Google Scholar 

  3. Barocci, M., Benini, L., Bogliolo, A., Ricco, B., Micheli, G.D.: Lookup Table Power Macro-Models for Behavioral Library Components. In: Puiri, V. (ed.) IEEE Alessandro Volta Memorial Workshop on Low-Power Design, pp. 173–181. IEEE, Piscataway (1999)

    Chapter  Google Scholar 

  4. Gupta, S., Najm, F.N.: Power Modeling for High-Level Power Estimation. IEEE Trans. VLSI Systems 8(1), 18–29 (2000)

    Article  Google Scholar 

  5. Bernacchia, G., Papaefthymiou, M.C.: Analytical Model for High-Level Power Estimation. In: White, J., Sentovich, E.M. (eds.) IEEE/ACM International Conference on Computer-Aided Design, pp. 280–283. IEEE, Piscataway (1999)

    Google Scholar 

  6. Gupta, S., Najm, F.N.: Analytical Models for RTL Power Estimation of Combinational and Sequential Circuits. IEEE Trans. CAD of Integrated Circuits and Systems 19(7), 808–814 (2000)

    Article  Google Scholar 

  7. Haykin, S.: Neural Networks: A Comprehensive Foundation, 2nd edn. Prentice-Hall, New York (1999)

    MATH  Google Scholar 

  8. Ding, C.-S., Wu, Q., Hsieh, C.-T., Pedram, M.: Stratified Random Sampling for Power Estimation. IEEE Trans. CAD of Integrated Circuits and Systems 17(6), 465–471 (1998)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. School of Electronics Information, Wuhan University, Luoyu Road 129, Wuhan, 430079, China

    Wei Qiang, Yang Cao, Yuan-yuan Yan & Xun Gao

Authors
  1. Wei Qiang
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Yang Cao
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Yuan-yuan Yan
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Xun Gao
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. Department of Mechanical and Automation Engineering, The Chinese University of Hong Kong, Shatin, New Territories, Hong Kong, China

    Jun Wang

  2. Computational Intelligence Laboratory, School of Computer Science and Engineering, University of Electronic Science and Technology of China, 610054, Chengdu, P.R. China

    Zhang Yi

  3. Department of Electrical Engineering, University of Louisville, 40292, Louisville, KY, U.S.A

    Jacek M. Zurada

  4. Laboratory for Computational Biology, Shanghai Center for Systems Biomedicine, 800 Dong Chuan Rd, 200240, Shanghai, China

    Bao-Liang Lu

  5. School of Electrical and Electronic Engineering, University of Manchester, UK

    Hujun Yin

Rights and permissions

Reprints and permissions

Copyright information

© 2006 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Qiang, W., Cao, Y., Yan, Yy., Gao, X. (2006). Power Estimation of CMOS Circuits by Neural Network Macromodel. In: Wang, J., Yi, Z., Zurada, J.M., Lu, BL., Yin, H. (eds) Advances in Neural Networks - ISNN 2006. ISNN 2006. Lecture Notes in Computer Science, vol 3973. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11760191_191

Download citation

  • DOI: https://doi.org/10.1007/11760191_191

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-34482-7

  • Online ISBN: 978-3-540-34483-4

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics

Search

Navigation