Abstract
Increasing the processor resources usability and boosting processor compatibility and capability to support multi-executions models in a single core are highly needed nowadays to benefit from the recent developments in electronics technology. This work introduces the concept of a dynamic switching mechanism (DSM), which supports multi-instruction set execution models in a single and simple processor core. This is achieved dynamically by execution mode–switching scheme and a sources–results locations computing unit for a novel queue execution model and a well-known stack based execution model. The queue execution model is based on queue computation that uses queue-registers, a circular queue data structure, for operands and results manipulations and assigns queue words according to a single assignment rule. We present the DSM mechanism and we describe its hardware complexity and preliminary evaluation results. We also describe the DSM target architecture.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Akanda, M.M., Abderazek, B.A., Yoshinaga, T., Sowa, M.: FaRMqs: Hybrid Processor Architecture in Verilog HDL. In: IPSJ 67th Conf., March 2 - 3 (2005); Parallel Execution in Parallel Queue Processor, IPSJ, 66th Conf., March 9 11, pp. 1–70 (2004)
Abderazek, B.A., Nikolova, K., Sowa, M.: FARM-Queue Mode: On a Practical Queue Execution Model. In: Proceedings of the Int. Conf. on Circuits and Systems, Computers and Communications, Tokushima, Japan, July 2001, pp. 939–944 (2001)
Sowa, M., Abderazek, B.A., Shigeta, S., Nikolova, K., Yoshinaga, T.: Proposal and Design of a Parallel Queue Processor Architecture (PQP). In: 14th IASTED Int. Conf. on Parallel and Distributed Computing and System, Cambridge, USA, November 2002, pp. 554–560 (2002)
VijayKrishnan, N.: Issues in the Design of JAVA Processor Architecture. PhD dissertation, University of South Florida, Tampa, FL-33620 (December 1998)
Radhakrishnan, R., Vijaykrishnan, N., John, L., Sivasubramanium, A.: Architectural issues in java runtime systems. Tech. Rep. TR-990719 (1999)
Sowa Laboratory, http://www.sowa.is.uec.ac.jp
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2005 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Musfiquzzaman, A.M., Abderazek, B.A., Kawata, S., Sowa, M. (2005). An Efficient Dynamic Switching Mechanism (DSM) for Hybrid Processor Architecture. In: Yang, L.T., Amamiya, M., Liu, Z., Guo, M., Rammig, F.J. (eds) Embedded and Ubiquitous Computing – EUC 2005. EUC 2005. Lecture Notes in Computer Science, vol 3824. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11596356_11
Download citation
DOI: https://doi.org/10.1007/11596356_11
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-30807-2
Online ISBN: 978-3-540-32295-5
eBook Packages: Computer ScienceComputer Science (R0)