Abstract
If adjacent wires are brought into a simple specific order of their switching activities, the effect of power optimal wire spacing can be increased. In this paper we will present this order along with a prove of this observation. For this purpose, it is shown how to derive the new power optimal wire positions by solving a geometric program. Due to their simplicity in implementation, both principles reported substantially differ from previous approaches. We also quantify the power optimization potential for wires based on a representative circuit model, with promising results.
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Boyd, S., Kim, S.J., Mohan, S.S.: Geometric Programming and its Applications to EDA Problems. Date 05 Tutorial Notes (2005)
Cong, J., Koh, C., Pan, Z.: Interconnect Sizing and Spacing with Consideration of Coupling Capacitance. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 6, 1164–1169 (2001)
Embacher, W.: Analysis of Automated Power Saving Techniques using Power Compiler (TM). LIS Diploma Thesis, TU München, Germany (May 2004)
Groeneveld, P.: Wire ordering for detailed routing. Design & Test of Computers 6, 6–17 (1989)
Ho, R., Mai, K.W., Horowitz, M.A.: The future of wires. Proceedings Of The IEEE 89(4), 490–504 (2001)
Computational Optimization Laboratory. A geometric programming solver, COPL GP (2000), Internet: http://www.stanford.edu/~yyye/Col.html
Macii, E., Poncino, M., Salerno, S.: Combining wire swapping and spacing for low-power deep-submicron buses. In: Proceedings of the 13th ACM Great Lakes symposium on VLSI, pp. 198–202 (2003)
Moiseev, K.: Net-Ordering for Optimal Circuit Timing in Nanometer Interconnect Design. CCIT Report #506, Haifa, Israel (October 2004)
Nabors, K.: FastCap. MIT, 1992 (2005)
Rockafellar, R.: Constrained Global Optimization: Algorithms and Applications. Springer, Heidelberg (1987)
SIA. International Technology Roadmap for Semiconductors (2005), Internet: http://public.itrs.net
Windschiegl, A., Stechele, W.: Exploiting metal layer characteristics for lowpower routing. In: Hochet, B., Acosta, A.J., Bellido, M.J. (eds.) PATMOS 2002. LNCS, vol. 2451, p. 55. Springer, Heidelberg (2002)
Zuber, P., Müller, F., Stechele, W.: Optimization Potential of CMOS Power by Wire Spacing. Lecture Notes in Informatics (2005)
Zuber, P., Windschiegl, A., Stechele, W.: Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization. Design, Automation & Test in Europe DATE (March 2005)
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© 2005 Springer-Verlag Berlin Heidelberg
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Zuber, P., Gritzmann, P., Ritter, M., Stechele, W. (2005). The Optimal Wire Order for Low Power CMOS. In: Paliouras, V., Vounckx, J., Verkest, D. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2005. Lecture Notes in Computer Science, vol 3728. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11556930_69
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DOI: https://doi.org/10.1007/11556930_69
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-29013-1
Online ISBN: 978-3-540-32080-7
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