Abstract
In this paper, we focus on engineering Pareto–optimal digital circuits given the expected input/output behaviour with a minimal design effort. The design objectives to be minimised are: hardware area, response time and power consumption. We do so using the Strength Pareto Evolutionary Algorithms. The performance and the quality of the circuit evolved for some benchmarks are presented then compared to those of single objective genetic algorithms as well as to the circuits obtained by human designers.
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Nedjah, N., de Macedo Mourelle, L. (2005). Pareto-Optimal Hardware for Digital Circuits Using SPEA. In: Ali, M., Esposito, F. (eds) Innovations in Applied Artificial Intelligence. IEA/AIE 2005. Lecture Notes in Computer Science(), vol 3533. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11504894_72
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DOI: https://doi.org/10.1007/11504894_72
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-26551-1
Online ISBN: 978-3-540-31893-4
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