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Power-efficient dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme

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Abstract

A novel dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme (DIFF-CGS) is proposed, which employs a transmission-gate-logic (TGL) based clock-gating scheme in the pulse generation stage. This scheme conditionally disables the inverter chain when the input data are kept unchanged, so redundant transitions of delayed clock signals and internal nodes of the latch are all eliminated, leading to low power efficiency. Based on SMIC 65 nm technology, extensive post-layout simulation results show that the proposed DIFF-CGS gains an improvement of 41.39% to 56.21% in terms of power consumption, compared with its counterparts at 10% data-switching activity. Also, full-swing operations in both implicit pulse generation and the static latch improve the robustness of the design. Thus, DIFF-CGS is suitable for low-power applications in very-large-scale integration (VLSI) designs with low data-switching activities.

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Authors and Affiliations

  1. College of Information Science & Electronic Engineering, Zhejiang University, Hangzhou, 310027, China

    Liang Geng, Ji-zhong Shen & Cong-yuan Xu

Authors
  1. Liang Geng
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  2. Ji-zhong Shen
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  3. Cong-yuan Xu
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Corresponding author

Correspondence to Ji-zhong Shen.

Additional information

Project supported by the National Natural Science Foundation of China (Nos. 61071062 and 61471314) and the Zhejiang Provincial Natural Science Foundation of China (No. LY13F010001)

ORCID: Ji-zhong SHEN, http://orcid.org/0000-0002-9031-2379

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Geng, L., Shen, Jz. & Xu, Cy. Power-efficient dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme. Frontiers Inf Technol Electronic Eng 17, 962–972 (2016). https://doi.org/10.1631/FITEE.1500293

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  • DOI: https://doi.org/10.1631/FITEE.1500293

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