A 10-bit 120MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) in 40-nm CMOS is presented. To diminish the fluctuation of common-mode voltage (VCM) and switching energy during conversion, a VCM-stable switching scheme is adopted without increasing the design complexity to V_CM buffers. Moreover, tri-switch sampling is employed in this design. Together with the binary-scaled recombination weighting (BSRW) method, it cancels the gain error and non-linearity caused by the parasitic input capacitor of comparators. The measurement results show that the reported ADC achieves an ENOB of 9.3 bits sampled at 120MS/s. The worst differential non-linearity (DNL) and integrated non-linearity (INL) are both below 0.5 LSB. The proposed ADC consumes 1.08-mW power, resulting in a figure of merit (FoM) of 14.3fJ/Conv.-step.