A store energy and latency reduction architecture based on proactive useless data flush (PUDF) is proposed for nonvolatile SRAM (NV-SRAM) using magnetic tunnel junctions (MTJs). Prior to the store operation to the MTJs in the array, the PUDF architecture predicts store-unneeded blocks having useless data and shuts down these blocks in advance. As a result, the store energy and latency can be reduced depending on the proportion of store-unneeded blocks, which enhances the energy reduction efficiency of power gating (PG) using the NV-SRAM. The energy and latency characteristics are computationally analysed and experimentally verified using circuit parameters extracted from fabricated test-element-group (TEG) circuits of the NV-SRAM.