This paper presents a low-voltage 3^rd-order single-bit switched-capacitor Σ-Δ modulator implemented in a 40-nm CMOS technology. In the modulator, a 2-tap FIR (finite impulse response) filter is employed in the feedback loop to reduce the integrator output swings. With the help of digital assisted techniques, the number of the sampling capacitors in the first integrator is reduced to mitigate the performance deterioration caused by capacitor mismatch. Besides, the inverter-based amplifiers with dynamic-biased structure are proposed to reduce the power consumption. The proposed modulator is sampled at 25.6 MHz over a bandwidth of 100 kHz. The modulator achieves a max SNR (signal-to-noise ratio) of 92.1 dB, a max SNDR (signal-to-noise and distortion ratio) of 87.3 dB, and a DR (dynamic range) of 88.1 dB under the supply voltage of ±0.45 V while consuming a total power consumption of 790 µW.