This paper presents a modified feed-forward (FF) delta-sigma modulator architecture that simplifies the switched-capacitor network of an analog adder in front of the quantizer. By eliminating the internal FF path from the first integrator output, the number of capacitors in the analog adder is reduced and the load capacitance of the first integrator becomes independent of the quantizer resolution. To verify the proposed modulator architecture, a three-bit second-order delta-sigma analog-to-digital converter (ADC) is implemented. The prototype ADC is fabricated in a 0.18 µm CMOS process with an active die area of 0.095 mm². It achieves a dynamic range (DR) of 101.0 dB and a peak signal-to-noise and distortion ratio (SNDR) of 97.1 dB in a 2 kHz signal bandwidth while consuming 63.4 µW from a 1.8 V/1.65 V power supply.