In this paper, we present an ultra-low voltage Advanced Encryption Standard (AES) SubBytes transformation (S-BOX) circuit. The S-BOX is widely used as a basic cryptographic primitive for the secure transaction in wireless sensor networks. We employ an asynchronous circuit design technique for low-voltage operations to achieve ultra-low power dissipation. In the proposed approach, we apply a quasi-delay-insensitive (QDI) design methodology to the asynchronous S-BOX circuit to reduce the spurious transitions in combinational logics and to increase robustness against PVT variations. Measurement results in 0.18-µm CMOS process demonstrated that our asynchronous S-BOX circuit consumes only 0.99-pJ at 330-mV, which is 12% less energy than that of synchronous one. QDI asynchronous circuits in the datapath are an effective solution in the near-threshold and sub-threshold regimes.