Design of low-power clock generator synchronized with AC power for adiabatic dynamic CMOS logic

LETTER

Seung-Il Cho, Seong-Kweon Kim, Tomochika Harada, Michio Yokoyama

Author information

Keywords: synchronization, low-power clock generator, adiabatic dynamic CMOS logic (ADCL), wave shaping circuit (WSC), asymmetry duty ratio divider (ADD)

JOURNAL FREE ACCESS

2013 Volume 10 Issue 20 Pages 20130716

DOI https://doi.org/10.1587/elex.10.20130716

Browse “Advance online publication” version

Details

Abstract

To reduce the power dissipation in conventional CMOS logic and to maintain adiabatic charging and discharging with low power for the adiabatic dynamic CMOS logic (ADCL), the clock signal of logic circuits should be synchronized with the AC power source. In this paper, the low-power clock generator synchronized with the AC power signal is proposed for ADCL system. From the simulation result, summation of power consumption of the designed wave shaping circuit (WSC) and asymmetry duty ratio divider (ADD) was estimated with approximately 1.197μW and 58.1μW at 3kHz and 10MHz, respectively.

Corresponding author

Register with J-STAGE for free!