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"Feasibility Study of High-Level Synthesis: Implementation of a Real-Time ..."

Panu Sjövall (2023)

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DOI: —

access: closed

type: Book or Thesis

metadata version: 2023-03-23

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Panu Sjövall:
Feasibility Study of High-Level Synthesis: Implementation of a Real-Time HEVC Intra Encoder on FPGA. University of Tampere, Finland, 2023

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