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Panu Sjövall
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2020 – today
- 2023
- [b1]Panu Sjövall:
Feasibility Study of High-Level Synthesis: Implementation of a Real-Time HEVC Intra Encoder on FPGA. University of Tampere, Finland, 2023 - [c12]Panu Sjövall
, Alexandre Mercat
FPGA-Accelerated HEVC Encoder for Energy-Efficient Multi-Access Edge Computing. ICIP 2023: 2215-2219 - 2022
- [j2]Panu Sjövall
High-Level Synthesis Implementation of an Embedded Real-Time HEVC Intra Encoder on FPGA for Media Applications. ACM Trans. Design Autom. Electr. Syst. 27(4): 35:1-35:34 (2022) - 2021
- [c11]Tero Partanen
High-Level Synthesis Implementation of Transform-Exempted SATD Architectures for Low-Power Video Coding. ISCAS 2021: 1-5 - [c10]Panu Sjövall
High-Level Synthesis Implementation of an Accurate HEVC Interpolation Filter on an FPGA. NorCAS 2021: 1-7
2010 – 2019
- 2019
- [j1]Sakari Lahti
Are We There Yet? A Study on the State of High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(5): 898-911 (2019) - [c9]Panu Sjövall
Dynamic Resource Allocation for HEVC Encoding in FPGA-Accelerated SDN Cloud. NORCAS 2019: 1-5 - [c8]Panu Sjövall
Visualization of Dynamic Resource Allocation for HEVC Encoding in FPGA-Accelerated SDN Cloud. VCIP 2019: 1-2 - 2018
- [c7]Panu Sjövall
FPGA-Powered 4K120p HEVC Intra Encoder. ISCAS 2018: 1-5 - [c6]Vili Viitamäki, Panu Sjövall
Live Demonstration: 4K100p HEVC Intra Encoder. ISCAS 2018: 1- - 2017
- [c5]Panu Sjovall
High-level synthesis implementation of HEVC 2-D DCT/DST on FPGA. ICASSP 2017: 1547-1551 - [c4]Vili Viitamäki, Panu Sjovall
High-level synthesized 2-D IDCT/IDST implementation for HEVC codecs on FPGA. ISCAS 2017: 1-4 - [c3]Panu Sjovall
Kvazaar 4K HEVC intra encoder on FPGA accelerated airframe server. SiPS 2017: 1-6 - 2016
- [c2]Janne Virtanen, Panu Sjovall
Distributed systemc simulation on manycore servers. NORCAS 2016: 1-6 - 2015
- [c1]Panu Sjovall
High-Level Synthesis Design Flow for HEVC Intra Encoder on SoC-FPGA. DSD 2015: 49-56
Coauthor Index
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