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"A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control ..."

Dong-Uk Lee et al. (2006)

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DOI: 10.1109/ISSCC.2006.1696091

access: closed

type: Conference or Workshop Paper

metadata version: 2020-06-09

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  - conf/isscc/LeeLKCMKKKKCMAK06
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Dong-Uk Lee, Hyun-Woo Lee, Ki Chang Kwean, Young-Kyoung Choi, Hyong Uk Moon, Seung-Wook Kwack, Shin-Deok Kang, Kwan-Weon Kim, Yong Ju Kim, Young-Jung Choi, Patrick B. Moran, Jin-Hong Ahn, Joong Sik Kih:
A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL. ISSCC 2006: 547-556

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