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Jin-Hong Ahn
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2000 – 2009
- 2009
- [c6]Bong Hwa Jeong, Jongwon Lee, Yin Jae Lee, Tae Jin Kang, Joo Hyeon Lee, Duck Hwa Hong, Jae Hoon Kim, Eun Ryeong Lee, Min Chang Kim, Kyung Ha Lee, Sang Il Park, Jong Ho Son, Sang Kwon Lee, Seong Nyuh Yoo, Sung Mook Kim, Tae Woo Kwon, Jin-Hong Ahn, Yong Tak Kim:
A 1.35V 4.3GB/s 1Gb LPDDR2 DRAM with controllable repeater and on-the-fly power-cut scheme for low-power and high-speed mobile application. ISSCC 2009: 132-133 - [c5]Hyun-Woo Lee, Won-Joo Yun, Young-Kyoung Choi, Hyang-Hwa Choi, Jong-Jin Lee, Ki-Han Kim, Shin-Deok Kang, Ji-Yeon Yang, Jae-Suck Kang, Hyeng-Ouk Lee, Dong-Uk Lee, Sujeong Sim, Young-Ju Kim, Won-Jun Choi, Keun-Soo Song, Sang-Hoon Shin, Hyung-Wook Moon, Seung-Wook Kwack, Jung-Woo Lee, Nak-Kyu Park, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, Byong-Tae Chung:
A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS. ISSCC 2009: 140-141 - 2008
- [c4]Won-Joo Yun, Hyun-Woo Lee, Dongsuk Shin, Shin-Deok Kang, Ji-Yeon Yang, Hyeng-Ouk Lee, Dong-Uk Lee, Sujeong Sim, Young-Ju Kim, Won-Jun Choi, Keun-Soo Song, Sang-Hoon Shin, Hyang-Hwa Choi, Hyung-Wook Moon, Seung-Wook Kwack, Jung-Woo Lee, Young-Kyoung Choi, Nak-Kyu Park, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, Ye Seok Yang:
A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology. ISSCC 2008: 282-283 - 2007
- [j3]Ki-Won Lee, Joo-Hwan Cho, Byoung-Jin Choi, Geun-Il Lee, Ho-Don Jung, Woo-Young Lee, Ki-Chon Park, Yongsuk Joo, Jaehoon Cha, Young-Jung Choi, Patrick B. Moran, Jin-Hong Ahn:
A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL. IEEE J. Solid State Circuits 42(11): 2369-2377 (2007) - 2006
- [c3]Dong-Uk Lee, Hyun-Woo Lee, Ki Chang Kwean, Young-Kyoung Choi, Hyong Uk Moon, Seung-Wook Kwack, Shin-Deok Kang, Kwan-Weon Kim, Yong Ju Kim, Young-Jung Choi, Patrick B. Moran, Jin-Hong Ahn, Joong Sik Kih:
A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL. ISSCC 2006: 547-556 - 2004
- [c2]Kyeong-Sik Min, Young-Hee Kim, Daejeong Kim, Dong Myeong Kim, Jin-Hong Ahn:
A large-current-output boosted voltage generator with non-overlapping clock control for sub-1-V memory applications. ASP-DAC 2004: 288-291 - 2002
- [j2]Se Jun Kim, Sang Hoon Hong, Jae-Kyung Wee, Joo-Hwan Cho, Pil Soo Lee, Jin-Hong Ahn, Jin-Yong Chung:
A low-jitter wide-range skew-calibrated dual-loop DLL using antifuse circuitry for high-speed DRAM. IEEE J. Solid State Circuits 37(6): 726-734 (2002) - [c1]Kyeong-Sik Min, Young-Hee Kim, Jin-Hong Ahn, Jin-Yong Chung, Takayasu Sakurai:
CMOS charge pumps using cross-coupled charge transfer switches with improved voltage pumping gain and low gate-oxide stress for low-voltage memory circuits. ISCAS (5) 2002: 545-548 - 2001
- [j1]Sung-Ho Wang, Jeongpyo Kim, Joonsuk Lee, Hyoung Sik Nam
, Young Gon Kim, Jae Hoon Shim, Hyung Ki Ahn, Seok Kang, Bong Hwa Jeong, Jin-Hong Ahn, Beomsup Kim:
A 500-Mb/s quadruple data rate SDRAM interface using a skew cancellation technique. IEEE J. Solid State Circuits 36(4): 648-657 (2001)
Coauthor Index
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