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2020 – today
- 2024
- [j37]Wei Chen
, Dake Liu
B5G/6G URLLC Latency Reduction Method for Multisensor Industrial Internet of Things. IEEE Internet Things J. 11(7): 11444-11459 (2024) - [j36]Wei Chen
Conflict-Free Parallel Data Access Technology for Matrix Calculation in Memory System of ASIP of 5G/6G Macro Base Stations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(1): 99-112 (2024) - 2023
- [c77]Guangzheng Fei
TAPE: Tangible Augmented Previz Environment for Filmmaking. CCHI 2023: 251-262 - 2022
- [j35]Wei Chen
Compilation of Parallel Data Access for Vector Processor in Radio Base Stations. IEEE Embed. Syst. Lett. 14(1): 11-14 (2022) - [j34]Biao Long
An Uplink Channel Estimator Using a Dedicated Instruction Set for 5G Small Cells. Sensors 22(3): 753 (2022) - [j33]Muxuan Gao, He Chen, Dake Liu:
An ASIP for Neural Network Inference on Embedded Devices with 99% PE Utilization and 100% Memory Hidden under Low Silicon Cost. Sensors 22(10): 3841 (2022) - [j32]Cao Niu
Detector Processor for a 5G Base Station. Sensors 22(20): 7731 (2022) - 2021
- [j31]Wei Chen
Design Space Exploration of SDR Vector Processor for 5G Micro Base Stations. IEEE Access 9: 141367-141377 (2021) - [j30]Yunxiang Tang, Biao Long, Dake Liu:
An ASIP design for low loss compression of front-haul data in 5G base stations. IEICE Electron. Express 18(4): 20200432 (2021) - [j29]Xiaokang Xiong
Hardware Sharing for Channel Interleavers in 5G NR Standard. Secur. Commun. Networks 2021: 8872140:1-8872140:13 (2021) - [j28]Yunke Tian
Low-Latency QC-LDPC Encoder Design for 5G NR. Sensors 21(18): 6266 (2021)
2010 – 2019
- 2019
- [j27]Shaohan Liu
A High-Flexible Low-Latency Memory-Based FFT Processor for 4G, WLAN, and Future 5G. IEEE Trans. Very Large Scale Integr. Syst. 27(3): 511-523 (2019) - 2018
- [j26]Wan Qiao
QFEC ASIP: A Flexible Quad-Mode FEC ASIP for Polar, LDPC, Turbo, and Convolutional Code Decoding. IEEE Access 6: 72189-72200 (2018) - [j25]Yuanhong Huo, Dake Liu:
High-throughput bit processor for cryptography, error correction, and error detection. Microprocess. Microsystems 61: 207-216 (2018) - [j24]Shaohan Liu, Dake Liu:
Design Space Exploration of 1-D FFT Processor. J. Signal Process. Syst. 90(11): 1609-1621 (2018) - 2017
- [j23]Chen Gong
An NFC on Two-Coil WPT Link for Implantable Biomedical Sensors under Ultra-Weak Coupling. Sensors 17(6): 1358 (2017) - [j22]Zhidong Miao
An Adaptive Impedance Matching Network with Closed Loop Control Algorithm for Inductive Wireless Power Transfer. Sensors 17(8): 1759 (2017) - [j21]Chen Gong
A Magnetic-Balanced Inductive Link for the Simultaneous Uplink Data and Power Telemetry. Sensors 17(8): 1768 (2017) - [j20]Zhidong Miao, Dake Liu, Chen Gong:
Efficiency Enhancement for an Inductive Wireless Power Transfer System by Optimizing the Impedance Matching Networks. IEEE Trans. Biomed. Circuits Syst. 11(5): 1160-1170 (2017) - [j19]Zhenzhi Wu, Chen Gong, Dake Liu:
Computational Complexity Analysis of FEC Decoding on SDR Platforms. J. Signal Process. Syst. 89(2): 209-224 (2017) - [c76]Yuanhong Huo, Dake Liu:
High-throughput area-efficient processor for 3GPP LTE cryptographic core algorithms. ASAP 2017: 210 - [c75]Min Li, Dake Liu, Chen Gong, Wan Qiao:
A 3-coil simultaneous power and uplink data transmission inductive link for battery-less implantable devices. ISCAS 2017: 1-4 - 2016
- [j18]Yuanhong Huo, Dake Liu:
A High-Throughput Processor for Cryptographic Hash Functions. J. Commun. 11(7): 702-709 (2016) - [c74]Hongxia Luo, Dake Liu, Chen Gong, Min Li:
A digital crystal-less clock generation scheme for wireless biomedical implants. BioCAS 2016: 480-483 - 2015
- [j17]Shanzhi Chen, Jian Zhao, Ming Ai, Dake Liu, Ying Peng:
Virtual RATs and a flexible and tailored radio access network evolving to 5G. IEEE Commun. Mag. 53(6-Supplement): 52-58 (2015) - [j16]Zhenzhi Wu, Dake Liu:
High-Throughput Trellis Processor for Multistandard FEC Decoding. IEEE Trans. Very Large Scale Integr. Syst. 23(12): 2757-2767 (2015) - [c73]Chen Gong, Dake Liu, Zhidong Miao, Huahong Zhang:
A novel transcutaneous NFC uplink system symbiotic with inductive wireless power supply under ultra low coupling coefficient. BioCAS 2015: 1-4 - [c72]Zhidong Miao, Dake Liu, Chen Gong:
An optimizing procedure of the wireless power transfer link for an intraocular implantable device. BMEI 2015: 338-343 - [c71]Muhammad Fahim Ul Haque, Ted Johansson
Combined RF and multiphase PWM transmitter. ECCTD 2015: 1-4 - [c70]Dake Liu, Chaoyuan Zuo, Zhenzhi Wu:
Benefit and cost of cross sliding window scheduling for low latency 5G Turbo decoding. ICCC 2015: 1-4 - [c69]Andreas Karlsson, Joar Sohl, Dake Liu:
ePUMA: A processor architecture for future DSP. DSP 2015: 253-257 - [c68]Andreas Karlsson, Joar Sohl, Dake Liu:
Cost-efficient mapping of 3- and 5-point DFTs to general baseband processors. DSP 2015: 780-784 - [c67]Andreas Karlsson, Joar Sohl, Dake Liu:
Software-based QPP interleaving for baseband DSPs with LUT-accelerated addressing. DSP 2015: 785-789 - [c66]Yuanhong Huo, Xiaoyang Li, Wei Wang, Dake Liu:
High performance table-based architecture for parallel CRC calculation. LANMAN 2015: 1-6 - [c65]Zhenzhi Wu, Dake Liu, Xiaoyang Li, Chen Gong:
A contention-free memory subsystem for 5G Turbo decoder with flexible degree of parallelism. SiPS 2015: 1-5 - [c64]Zhenzhi Wu, Dake Liu, Xiaoyang Li:
Loop acceleration and instruction repeat support for application specific instruction-set processors. SoCC 2015: 251-256 - [c63]Andreas Karlsson, Joar Sohl, Dake Liu:
Energy-Efficient Sorting with the Distributed Memory Architecture ePUMA. TrustCom/BigDataSE/ISPA (3) 2015: 116-123 - 2014
- [j15]Siye Wang, Yanjun Zhang
Comprehensive Performance Analysis of Two-Way Multi-Relay System with Amplify-and-Forward Relaying. IEICE Trans. Commun. 97-B(3): 666-673 (2014) - [j14]Shanzhi Chen, Hui Xu, Dake Liu, Bo Hu, Hucheng Wang:
A Vision of IoT: Applications, Challenges, and Opportunities With China Perspective. IEEE Internet Things J. 1(4): 349-359 (2014) - [c62]Zhenzhi Wu, Dake Liu:
Flexible multistandard FEC processor design with ASIP methodology. ASAP 2014: 210-218 - [c61]Zhenzhi Wu, Dake Liu, Zheng Yang, Qingying Wang, Wei Zhou:
FPGA implementation of a multi-algorithm parallel FEC for SDR platforms. FPL 2014: 1-6 - [c60]Zhenzhi Wu, Dake Liu, Yanjun Zhang:
Matrix reordering techniques for memory conflict reduction for pipelined QC-LDPC decoder. ICCC 2014: 354-359 - [c59]Xiaoyang Li, Yu Liu, Chen Gong, Dake Liu:
Recognition of access patterns for DSP kernel codes. ICSAI 2014: 334-338 - [c58]Zhenzhi Wu, Dake Liu:
Memory sharing techniques for multi-standard high-throughput FEC decoder. ICSAMOS 2014: 93-98 - [c57]Chen Gong, Xiaoyang Li, Zhenzhi Wu, Dake Liu:
A conflict-free access method for parallel turbo decoder. WCSP 2014: 1-6 - 2013
- [j13]Wenbiao Zhou, Zhaoyun Cai, Ruiqiang Ding, Chen Gong, Dake Liu:
Efficient sorting design on a novel embedded parallel computing architecture with unique memory access. Comput. Electr. Eng. 39(7): 2100-2111 (2013) - [j12]Xu Yang, Yanjun Zhang, Dake Liu, Deyuan Guo, Hu He:
Single instruction multiple data code auto generation for a very long instruction words digital signal processor in sensor-based systems. IET Wirel. Sens. Syst. 3(2) (2013) - [c56]Andreas Karlsson, Joar Sohl, Jian Wang, Dake Liu:
ePUMA: A unique memory access based parallel DSP processor for SDR and CR. GlobalSIP 2013: 1234-1237 - [c55]Joar Sohl, Jian Wang, Andreas Karlsson, Dake Liu:
Conflict-free data access for multi-bank memory architectures using padding. HiPC 2013: 425-432 - [c54]Muhammad Fahim Ul Haque, Ted Johansson
Combined RF and multilevel PWM switch mode power amplifier. NORCHIP 2013: 1-4 - [p2]Dake Liu, Jian Wang:
Application Specific Instruction Set DSP Processors. Handbook of Signal Processing Systems 2013: 671-706 - 2012
- [j11]Rizwan Asghar, Di Wu, Ali Saeed, Yulin Huang, Dake Liu:
Implementation of a Radix-4, Parallel Turbo Decoder and Enabling the Multi-Standard Support. J. Signal Process. Syst. 66(1): 25-41 (2012) - [c53]Wenbiao Zhou, Per Karlström, Dake Liu:
Automatic Synthesizable HDL Generator for NoGAP. ACIS-ICIS 2012: 119-123 - [c52]Jian Wang, Andreas Karlsson, Joar Sohl, Dake Liu:
Convolutional Decoding on Deep-pipelined SIMD Processor with Flexible Parallel Memory. DSD 2012: 529-532 - [c51]Joar Sohl, Jian Wang, Andreas Karlsson, Dake Liu:
Automatic Permutation for Arbitrary Static Access Patterns. ISPA 2012: 215-222 - 2011
- [j10]Di Wu, Johan Eilert, Dake Liu:
Implementation of a High-Speed MIMO Soft-Output Symbol Detector for Software Defined Radio. J. Signal Process. Syst. 63(1): 27-37 (2011) - [c50]Dake Liu, Andreas Karlsson, Joar Sohl, Jian Wang, Magnus Pettersson, Wenbiao Zhou:
ePUMA embedded parallel DSP processor with Unique Memory Access. ICICS 2011: 1-5 - [c49]Jian Wang, Andreas Karlsson, Joar Sohl, Magnus Pettersson, Dake Liu:
A multi-level arbitration and topology free streaming network for chip multiprocessor. ASICON 2011: 153-158 - [c48]Erik Hansson, Joar Sohl, Christoph W. Kessler, Dake Liu:
Case Study of Efficient Parallel Memory Access Programming for the Embedded Heterogeneous Multicore DSP Architecture ePUMA. CISIS 2011: 624-629 - [c47]Michal Simko, Di Wu, Christian Mehlführer, Johan Eilert, Dake Liu:
Implementation Aspects of Channel Estimation for 3GPP LTE Terminals. EW 2011 - [c46]Jian Wang, Joar Sohl, Andreas Karlsson, Dake Liu:
An Efficient Streaming Star Network for Multi-core Parallel DSP Processor. ICNC 2011: 332-336 - 2010
- [j9]Di Wu, Johan Eilert, Rizwan Asghar, Dake Liu:
VLSI Implementation of a Fixed-Complexity Soft-Output MIMO Detector for High-Speed Wireless. EURASIP J. Wirel. Commun. Netw. 2010 (2010) - [j8]Dake Liu, Joar Sohl, Jian Wang:
Parallel Programming and Its Architectures Based on Data Access Separated Algorithm Kernels. Int. J. Embed. Real Time Commun. Syst. 1(1): 64-85 (2010) - [j7]Di Wu, Johan Eilert, Rizwan Asghar, Dake Liu, Anders Nilsson, Eric Tell, Eric Alfredsson:
System Architecture for 3GPP-LTE Modem using a Programmable Baseband Processor. Int. J. Embed. Real Time Commun. Syst. 1(3): 44-64 (2010) - [j6]Rizwan Asghar, Dake Liu:
Multimode Flex-Interleaver Core for Baseband Processor Platform. J. Comput. Networks Commun. 2010: 793807:1-793807:16 (2010) - [j5]Rizwan Asghar, Di Wu, Johan Eilert, Dake Liu:
Memory Conflict Analysis and Implementation of a Re-configurable Interleaver Architecture Supporting Unified Parallel Turbo Decoding. J. Signal Process. Syst. 60(1): 15-29 (2010) - [c45]Wenbiao Zhou, Per Karlström, Dake Liu:
NoGapCL: A flexible common language for processor hardware description. DDECS 2010: 225-228 - [c44]Jian Wang, Joar Sohl, Olof Kraigher, Dake Liu:
Software Programmable Data Allocation in Multi-bank Memory of SIMD Processors. DSD 2010: 28-33 - [c43]Jian Wang, Joar Sohl, Dake Liu:
Architectural Support for Reducing Parallel Processing Overhead in an Embedded Multiprocessor. EUC 2010: 47-52 - [c42]Per Karlström, Wenbiao Zhou, Dake Liu:
Implementation of a Floating Point Adder and Subtracter in NoGAP, A Comparative Case Study. EUC 2010: 68-72 - [c41]Per Karlström, Wenbiao Zhou, Dake Liu:
Operation Classification for Control Path Synthetization with NoGAP. ITNG 2010: 1195-1200 - [c40]Per Karlström, Wenbiao Zhou, Dake Liu:
Automatic port and bus sizing in NoGap. ICSAMOS 2010: 258-264 - [c39]Di Wu, Johan Eilert, Rizwan Asghar, Dake Liu, Magic Ge:
VLSI implementation of A multi-standard MIMO symbol detector for 3GPP LTE and WiMAX. WTS 2010: 1-4 - [p1]Dake Liu:
Application Specific Instruction Set DSP Processors. Handbook of Signal Processing Systems 2010: 415-447
2000 – 2009
- 2009
- [j4]Dake Liu, Anders Nilsson, Eric Tell, Di Wu, Johan Eilert:
Bridging dream and reality: Programmable baseband processors for software-defined radio. IEEE Commun. Mag. 47(9): 134-140 (2009) - [j3]Anders Nilsson, Eric Tell, Dake Liu:
An 11 mm2, 70 mW Fully Programmable Baseband Processor for Mobile WiMAX and DVB-T/H in 0.12µm CMOS. IEEE J. Solid State Circuits 44(1): 90-97 (2009) - [c38]Joar Sohl, Jian Wang, Dake Liu:
Large Matrix Multiplication on a Novel Heterogeneous Parallel DSP Architecture. APPT 2009: 408-419 - [c37]Rizwan Asghar, Di Wu, Johan Eilert, Dake Liu:
Memory Conflict Analysis and Interleaver Design for Parallel Turbo Decoding Supporting HSPA Evolution. DSD 2009: 699-706 - [c36]Di Wu, Johan Eilert, Dake Liu:
Evaluation of MIMO symbol detectors for 3GPP LTE terminals. EUSIPCO 2009: 2431-2435 - [c35]Andreas Ehliar, Dake Liu:
An ASIC perspective on FPGA optimizations. FPL 2009: 218-223 - [c34]Rizwan Asghar, Dake Liu:
Low Complexity Hardware Interleaver for MIMO-OFDM based Wireless LAN. ISCAS 2009: 1747-1750 - [c33]Di Wu, Johan Eilert, Dake Liu, Anders Nilsson, Eric Tell, Eric Alfredsson:
System architecture for 3GPP LTE modem using a programmable baseband processor. SoC 2009: 132-137 - [c32]Per Karlström, Dake Liu:
NoGAP: A Micro Architecture Construction Framework. SAMOS 2009: 171-180 - [c31]Di Wu, Erik G. Larsson, Dake Liu:
Implementation Aspects of Fixed-Complexity Soft-Output MIMO Detection. VTC Spring 2009 - 2008
- [j2]Per Karlström, Andreas Ehliar, Dake Liu:
High-performance, low-latency field-programmable gate array-based floating-point adder and multiplier units in a Virtex 4. IET Comput. Digit. Tech. 2(4): 305-313 (2008) - [c30]Andreas Ehliar, Per Karlström, Dake Liu:
A high performance microprocessor with DSP extensions optimized for the Virtex-4 FPGA. FPL 2008: 599-602 - [c29]Johan Eilert, Di Wu, Dake Liu:
Implementation of a programmable linear MMSE detector for MIMO-OFDM. ICASSP 2008: 5396-5399 - [c28]Anders Nilsson, Eric Tell, Dake Liu:
An 11mm2 70mW Fully-Programmable Baseband Processor for Mobile WiMAX and DVB-T/H in 0.12μm CMOS. ISSCC 2008: 266-267 - [c27]Rizwan Asghar, Dake Liu:
Dual standard re-configurable hardware interleaver for turbo decoding. ISWPC 2008: 768-772 - [c26]Qi Wang, Di Wu, Johan Eilert, Dake Liu:
Cost Analysis of Channel Estimation in MIMO-OFDM for Software Defined Radio. WCNC 2008: 935-939 - 2007
- [c25]Andreas Ehliar, Dake Liu:
An fpga based open source network-on-chip architecture. FPL 2007: 800-803 - [c24]Johan Eilert, Di Wu, Dake Liu:
Efficient Complex Matrix Inversion for MIMO Software Defined Radio. ISCAS 2007: 2610-2613 - [c23]Di Wu, Johan Eilert, Dake Liu, Dandan Wang, Naofal Al-Dhahir, Hlaing Minn:
Fast Complex Valued Matrix Inversion for Multi-User STBC-MIMO Decoding. ISVLSI 2007: 325-330 - [c22]Di Wu, Johan Eilert, Dake Liu:
Lattice-Reduction Aided Multi-User STBC Decoding with Resource Constraints. PIMRC 2007: 1-5 - [c21]Anders Nilsson, Dake Liu:
Area Efficient Fully Programmable Baseband Processors. SAMOS 2007: 333-342 - 2006
- [c20]Di Wu, Tiejun Hu, Dake Liu:
A Single Issue DSP based Multi-standard Media Processor for Mobile Platforms. ARCS Workshops 2006: 333-342 - [c19]Oskar Flordal, Di Wu, Dake Liu:
Accelerating CABAC encoding for multi-standard media with configurability. IPDPS 2006 - [c18]Haiyan Jiao, Anders Nilsson, Eric Tell, Dake Liu:
MIPS cost estimation for OFDM-VBLAST systems. WCNC 2006: 822-826 - 2005
- [c17]Andreas Ehliar, Dake Liu:
Flexible route lookup using range search. Communications and Computer Networks 2005: 345-350 - [c16]Anders Nilsson, Eric Tell, Dake Liu:
A programmable SIMD-based multi-standard Rake receiver architecture. EUSIPCO 2005: 1-4 - [c15]Daniel Wiklund, Dake Liu:
Design Mapping, and Simulations of a 3G WCDMA/FDD Basestation Using Network on Chip. IWSOC 2005: 252-256 - [c14]Eric Tell, Anders Nilsson, Dake Liu:
A Low Area and Low Power Programmable Baseband Processor Architecture. IWSOC 2005: 347-351 - 2004
- [c13]Mikael Olausson, Andreas Ehliar, Johan Eilert, Dake Liu:
Reduced floating point for MPEG1/2 layer III decoding. ICASSP (5) 2004: 209-212 - [c12]Sumant Sathe, Daniel Wiklund, Dake Liu:
Design of a guaranteed throughput router for on-chip networks. SoC 2004: 25-28 - [c11]Mikael Olausson, Anders Edman, Dake Liu:
Bit Memory Instructions for a General CPU. IWSOC 2004: 215-218 - [c10]Daniel Wiklund, Sumant Sathe, Dake Liu:
Network on Chip Simulations for Benchmarking. IWSOC 2004: 269-274 - [c9]Johan Eilert, Andreas Ehliar, Dake Liu:
Using low precision floating point numbers to reduce memory cost for MP3 decoding. MMSP 2004: 119-122 - [c8]Xiaoning Nie, Ulf Nordqvist, Lajos Gazsi, Dake Liu:
Network processors for access network (NP4AN): trends and challenges. SoCC 2004: 265-269 - 2003
- [c7]Tomas Henriksson, Dake Liu:
Implementation of fast CRC calculation. ASP-DAC 2003: 563-564 - [c6]Eric Tell, Mikael Olausson, Dake Liu:
A general DSP processor at the cost of 23K gates and 1/2 a man-year design time. ICASSP (2) 2003: 657-660 - [c5]Ulf Nordqvist, Dake Liu:
Power optimized packet buffering in a protocol processor. ICECS 2003: 1026-1029 - [c4]Daniel Wiklund, Dake Liu:
SoCBUS: Switched Network on Chip for Hard Real Time Embedded Systems. IPDPS 2003: 78 - [c3]Eric Tell, Olle Seger, Dake Liu:
A converged hardware solution for FFT, DCT and Walsh transform. ISSPA (1) 2003: 609-612 - 2002
- [c2]Tomas Henriksson, Ulf Nordqvist, Dake Liu:
Embedded Protocol Processor for Fast and Efficient Packet Reception. ICCD 2002: 414- - 2001
- [c1]Tomas Henriksson, Henrik Eriksson, Ulf Nordqvist, Per Larsson-Edefors, Dake Liu:
VLSI implementation of CRC-32 for 10 Gigabit Ethernet. ICECS 2001: 1215-1218
1990 – 1999
- 1994
- [j1]Dake Liu, Christer Svensson:
Power consumption estimation in CMOS VLSI chips. IEEE J. Solid State Circuits 29(6): 663-670 (1994)
Coauthor Index
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last updated on 2024-08-05 21:17 CEST by the dblp team
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