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Beomsup Kim
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2010 – 2019
- 2017
- [j24]Yashar Rajavi
, Mohammad Mahdi Ghahramani, Alireza Khalili, Amirpouya Kavousian, Beomsup Kim, Michael P. Flynn:
A 48-MHz Differential Crystal Oscillator With 168-fs Jitter in 28-nm CMOS. IEEE J. Solid State Circuits 52(10): 2735-2745 (2017) - 2012
- [j23]Shen Wang, Vipul Chawla, Dong Sam Ha, Beomsup Kim:
Low-Voltage Low-Power 1.6 GHz Quadrature Signal Generation Through Stacking a Transformer-Based VCO and a Divide-by-Two. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(12): 2901-2910 (2012) - 2011
- [c15]Shen Wang, Dong Sam Ha, Beomsup Kim, Vipul Chawla:
A combined VCO and divide-by-two for low-voltage low-power 1.6 GHz quadrature signal generation. CICC 2011: 1-4
2000 – 2009
- 2005
- [j22]Seok Kang, Beomsup Kim:
A DLL-Based Frequency Synthesizer with Selective Reuse of a Delay Cell Scheme for 2.4 GHz ISM Band. IEICE Trans. Electron. 88-C(1): 149-153 (2005) - [j21]Jaesang Lim, Jaejoon Kim
Analysis and Design of Multistage Low-Phase-Noise CMOS LC-Ring Oscillators. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(4): 1084-1089 (2005) - [j20]Jaesang Lim, Yongchul Song, Jeong Pyo Kim, Beomsup Kim:
An Efficient Software-Defined Radio Architecture for Multi-Mode WCDMA Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3677-3680 (2005) - [j19]Jinwook Kim, Jeongsik Yang, Sangjin Byun
A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer. IEEE J. Solid State Circuits 40(2): 462-471 (2005) - [j18]Jae Hoon Shim, In-Cheol Park, Beomsup Kim:
A third-order ΣΔ modulator in 0.18-μm CMOS with calibrated mixed-mode integrators. IEEE J. Solid State Circuits 40(4): 918-925 (2005) - [j17]Jae Hoon Shim, In-Cheol Park
Correction to "A Third-Order$Sigma Delta $Modulator in 0.18-$muhboxm$CMOS With Calibrated Mixed-Mode Integrators". IEEE J. Solid State Circuits 40(11): 2339 (2005) - [j16]Jae Hoon Shim, In-Cheol Park, Beomsup Kim:
Hybrid ΣΔ modulators with adaptive calibration. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(5): 885-893 (2005) - 2004
- [j15]Yongchul Song, Beomsup Kim:
A 14-b direct digital frequency synthesizer with sigma-delta noise shaping. IEEE J. Solid State Circuits 39(5): 847-851 (2004) - [j14]Yongchul Song, Beomsup Kim:
A quadrature digital synthesizer/mixer architecture using fine/coarse coordinate rotation to achieve 14-b input, 15-b output, and 100-dBc SFDR. IEEE J. Solid State Circuits 39(11): 1853-1861 (2004) - [j13]Yongchul Song, Beomsup Kim:
Quadrature direct digital frequency synthesizers using interpolation-based angle rotation. IEEE Trans. Very Large Scale Integr. Syst. 12(7): 701-710 (2004) - 2003
- [j12]Sangjin Byun
A low-power CMOS Bluetooth RF transceiver with a digital offset canceling DLL-based GFSK demodulator. IEEE J. Solid State Circuits 38(10): 1609-1618 (2003) - [j11]Yongchul Song, Beomsup Kim:
Low-jitter digital timing recovery techniques for CAP-based VDSL applications. IEEE J. Solid State Circuits 38(10): 1649-1656 (2003) - [c14]Yongchul Song, Beomsup Kim:
A 330-MHz 15-b quadrature digital synthesizer/mixer in 0.25-μm CMOS. ESSCIRC 2003: 513-516 - [c13]Hyung Ki Ahn, In-Cheol Park
A 5-GHz self-calibrated I/Q clock generator using a quadrature LC-VCO. ISCAS (1) 2003: 797-800 - [c12]Jae Hoon Shim, In-Cheol Park
A hybrid delta-sigma modulator with adaptive calibration. ISCAS (1) 2003: 1025-1028 - 2001
- [j10]Sung-Ho Wang, Jeongpyo Kim, Joonsuk Lee, Hyoung Sik Nam
A 500-Mb/s quadruple data rate SDRAM interface using a skew cancellation technique. IEEE J. Solid State Circuits 36(4): 648-657 (2001) - [j9]Chan-Hong Park, Ook Kim, Beomsup Kim:
A 1.8-GHz self-calibrated phase-locked loop with precise I/Q matching. IEEE J. Solid State Circuits 36(5): 777-783 (2001) - [c11]Yongchul Song, Kyehyung Lee, Beomsup Kim:
Digital timing synchronization with jitter reduction technique for cap-based VDSL system. ICASSP 2001: 2325-2328 - 2000
- [j8]Kyoohyun Lim, Chan-Hong Park, Dal-Soo Kim, Beomsup Kim:
A low-noise phase-locked loop design by loop bandwidth optimization. IEEE J. Solid State Circuits 35(6): 807-815 (2000) - [j7]Joonsuk Lee, Beomsup Kim:
A low-noise fast-lock phase-locked loop with adaptive bandwidth control. IEEE J. Solid State Circuits 35(8): 1137-1145 (2000) - [j6]Jae Joon Kim
A low-jitter mixed-mode DLL for high-speed DRAM applications. IEEE J. Solid State Circuits 35(10): 1430-1436 (2000) - [c10]Beomsup Kim, Joonsuk Lee, Seung Hee Choi, Jun Mo Koo, Byung Jun Min:
Non-Data-Aided Timing Recovery Algorithm for \pi/4-OPSK Modulated Signals. ICC (1) 2000: 392-396
1990 – 1999
- 1999
- [j5]Chan-Hong Park, Beomsup Kim:
A low-noise, 900-MHz VCO in 0.6-μm CMOS. IEEE J. Solid State Circuits 34(5): 586-591 (1999) - [c9]Tae Hun Kim, Jeongsik Yang, Kyoo Hyun Lim, Jin Wook Kim, Jeong Eun Lee, Hyoung Sik Nam, Young Gon Kim, Jeong Pyo Kim, Sangjin Byun
16-bit DSP and System for Baseband / Voiceband Processing of IS-136 Cellular Telephony. ASP-DAC 1999: 49- - 1998
- [j4]Chang-Hyun Kim, Jung-Hwa Lee, J. B. Lee, Beomsup Kim, C. S. Park, Sang-Bo Lee, S. Y. Lee, C. W. Park, J. G. Roh, Hyoung Sik Nam
A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system. IEEE J. Solid State Circuits 33(11): 1703-1710 (1998) - [c8]Tae Hun Kim, Beomsup Kim:
Dual-loop Digital PLL Design for Adaptive Clock Recovery. ASP-DAC 1998: 347-352 - 1997
- [j3]Seog-Jun Lee, Beomsup Kim, Kwyro Lee:
A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme. IEEE J. Solid State Circuits 32(2): 289-291 (1997) - [j2]Seog-Jun Lee, Beomsup Kim, Kwyro Lee:
A fully integrated low-noise 1-GHz frequency synthesizer design for mobile communication application. IEEE J. Solid State Circuits 32(5): 760-765 (1997) - [j1]Byungjin Chun, Yong Hoon Lee, Beomsup Kim:
Design of variable loop gains of dual-loop DPLL. IEEE Trans. Commun. 45(12): 1520-1522 (1997) - [c7]Kyoohyun Lim, Seung Hee Choi, Beomsup Kim:
Optimal loop bandwidth design for low noise PLL applications. ASP-DAC 1997: 425-428 - [c6]Byungjin Chun, Seung Hee Choi, Beomsup Kim:
A Digital Phase-Locked Loop with Variable Loop Gains Derived from RLS Method. ICC (1) 1997: 11-15 - 1995
- [c5]Jeongsik Yang, Chanhong Park, Beomsup Kim:
A digital audio signal processor for cellular phone application. ASP-DAC 1995 - [c4]Byungjin Chun, Beomsup Kim, Yong Hong Lee:
Adaptive Carrier Recovery Using Multi-Order DPLL for Mobile Communication Applications. ISCAS 1995: 1082-1085 - 1994
- [c3]Todd C. Weigandt, Beomsup Kim, Paul R. Gray:
Analysis of Timing Jitter in CMOS Ring Oscillators. ISCAS 1994: 27-30 - [c2]Beomsup Kim, Todd C. Weigandt, Paul R. Gray:
PLL/DLL System Noise Analysis for Low Jitter Clock Synthesizer Design. ISCAS 1994: 31-34 - 1993
- [c1]Beomsup Kim:
Optical MMSE gear-shifting algorithm for the fast synchronization of DPLL. ISCAS 1993: 172-175
Coauthor Index
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