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Yutaka Mori
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2010 – 2019
- 2018
- [c5]Yutaka Mori, Kosuke Yamashita, Masahiko Jinno:
Feasibility Demonstration of Integrated Fractioanal Joint Switching WSS Applicable for Few-Mode Multicore Fiber. PSC 2018: 1-3 - 2017
- [j3]Masahiko Jinno, Yutaka Mori:
Unified Architecture of an Integrated SDM-WSS Employing a PLC-Based Spatial Beam Transformer Array for Various Types of SDM Fibers. JOCN 9(2): A198-A206 (2017) - 2016
- [j2]Masahiko Jinno, Takuya Nakagawa, Yutaka Mori, Koichi Maru, Haruna Matsushita:
Effects of Adding/Dropping Nyquist WDM Superchannels on Linear and Nonlinear Transmission Impairments in an Elastic Optical Network. IEICE Trans. Commun. 99-B(8): 1669-1676 (2016) - [c4]Masahiko Jinno, Yutaka Mori:
Unified architecture and design methodology for integrated SDM-WSS employing PLC-based spatial beam transformer array for various types of SDM fibers. OFC 2016: 1-3 - 2015
- [c3]Takuya Nakagawa, Yutaka Mori, Koichi Maru, Haruna Matsushita, Masahiko Jinno:
Linear and nonlinear impairments when adding and dropping superchannels in an elastic optical network. APCC 2015: 25-28
2000 – 2009
- 2006
- [c2]Noriyuki Ito, Hideaki Katagiri, Ryoichi Yamashita, Hiroshi Ikeda, Hiroyuki Sugiyama, Hiroaki Komatsu, Yoshiyasu Tanamura, Akihiro Yoshitake, Kazuhiro Nonomura, Kinya Ishizaka, Hiroaki Adachi, Yutaka Mori, Yutaka Isoda, Yaroku Sugiyama:
Diagonal routing in high performance microprocessor design. ASP-DAC 2006: 624-629 - [c1]Jun Yamada, Hiroyuki Adachi, Yutaka Mori, Akihiko Harada, Seishi Okada, Hisashige Ando:
High-Speed Interconnect for a Multiprocessor Server Using Over 1Tb/s Crossbar. ISSCC 2006: 343-352
1990 – 1999
- 1995
- [j1]Vasily G. Moshnyaga, Yutaka Mori, Keikichi Tamaru:
Register-Transfer Module Selection for Sub-Micron ASIC Design. IEICE Trans. Inf. Syst. 78-D(3): 252-255 (1995)
Coauthor Index
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