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Harald Homulle
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- affiliation: Delft University of Technology, Netherlands
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2010 – 2019
- 2019
- [c10]Mohammadreza Mehrpoo, Bishnu Patra
, Jiang Gong, Pascal Alexander 't Hart, Jeroen P. G. van Dijk, Harald Homulle
Benefits and Challenges of Designing Cryogenic CMOS RF Circuits for Quantum Computers. ISCAS 2019: 1-5 - 2018
- [j2]Bishnu Patra
Cryo-CMOS Circuits and Systems for Quantum Computing Applications. IEEE J. Solid State Circuits 53(1): 309-321 (2018) - 2017
- [c9]Fabio Sebastiano, Harald Homulle
Cryo-CMOS Electronic Control for Scalable Quantum Computing: Invited. DAC 2017: 13:1-13:6 - [c8]Rosario M. Incandela, Lin Song, Harald A. R. Homulle
Nanometer CMOS characterization and compact modeling at deep-cryogenic temperatures. ESSDERC 2017: 58-61 - [c7]Harald Homulle
Performance characterization of Altera and Xilinx 28 nm FPGAs at cryogenic temperatures. FPT 2017: 25-31 - [c6]Edoardo Charbon, Fabio Sebastiano
15.5 Cryo-CMOS circuits and systems for scalable quantum computing. ISSCC 2017: 264-265 - [c5]Fabio Sebastiano
Cryogenic CMOS interfaces for quantum devices. IWASI 2017: 59-62 - 2016
- [j1]Harald Homulle
A Cryogenic 1 GSa/s, Soft-Core FPGA ADC for Quantum Computing Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(11): 1854-1865 (2016) - [c4]Harald Homulle
CryoCMOS hardware technology a classical infrastructure for a scalable quantum computer. Conf. Computing Frontiers 2016: 282-287 - [c3]Stefan Visser, Harald Homulle, Edoardo Charbon:
A 1 GSa/s, Reconfigurable Soft-core FPGA ADC (Abstract Only). FPGA 2016: 281 - [c2]Lin Song, Harald Homulle
Characterization of bipolar transistors for cryogenic temperature sensors in standard CMOS. IEEE SENSORS 2016: 1-3 - 2015
- [c1]Harald Homulle
200 MS/s ADC implemented in a FPGA employing TDCs. FPGA 2015: 228-235
Coauthor Index
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